Semiconductor memory with hierarchical bit lines

Static information storage and retrieval – Systems using particular element – Capacitors

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Details

365 63, 365 72, 36523003, G11C 1124, G11C 506

Patent

active

055616267

ABSTRACT:
A semiconductor memory with hierarchical bit lines has a plurality of local bit lines, a plurality of global bit lines, a plurality of word lines, a plurality of memory cells each arranged at a connection portion between each local bit line and each word line, and a plurality of transfer gates. The local bit lines are connected to the global bit line through the transfer gates, which are arranged near the centers of the local bit lines. This arrangement realizes a high-speed operation and a low power consumption without increasing the number of local, bit lines.

REFERENCES:
patent: 5367488 (1994-11-01), An
patent: 5495440 (1996-02-01), Asakura

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