Semiconductor memory with data detection circuit

Static information storage and retrieval – Read/write circuit – For complementary information

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Details

307238, G11C 706

Patent

active

041033450

ABSTRACT:
Provided is a semiconductor memory device comprising a pair of data input lines, a pair of data output lines, memory cells arranged in the form of a matrix, the memory cell of each column being connected between a pair of data lines, the memory cell of each row being connected to a row selection line, a memory cell selection circuit for generating column and row designation signals in order to select a desired one of said memory cells, a switching circuit disposed in each column and turned on upon receipt of a column designation signal from the memory cell selection circuit to connect the data line to a corresponding one of the data input lines, and a data detection circuit connected between the pair of data lines of each column and adapted, upon receipt of a column signal from the memory cell selection circuit, to transmit an inverted signal of a signal on the data line onto the data output line.

REFERENCES:
patent: 3720922 (1973-03-01), Kosonocky
patent: 3778782 (1973-12-01), Kitagawa
patent: 3838295 (1974-09-01), Lindell
patent: 3964031 (1976-06-01), Eaton, Jr.
patent: 3980899 (1976-09-01), Shimada et al.
patent: 4045785 (1977-08-01), Kirkpatrick, Jr.

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