Semiconductor memory with cells combined into individually addre

Details Semiconductor memory with cells combined into individually addre Semiconductor memory with cells combined into individually addre

1996-03-04

1997-09-23

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523003, 36523006, G11C 800

Patent

active

056711840

ABSTRACT:
Memory cells of a semiconductor memory are combined into individually addressable units. An address decoding circuit connects to the units. A programmable address transformation configuration is connected between address terminals receiving external address signals and the decoding circuit. The address transformation configuration, in its unprogrammed state, outputs an internal address signal at each of the outputs which corresponds to the external address signal present at a corresponding one of the address terminals. In its programmed state it outputs an internal address signal at at least one of said outputs, which differs from the external address signal present at a corresponding one of the inputs. The units are thus readdressed relative to the external address. The semiconductor memory is operated by applying external address signals for addressing the units at the address terminals; the external address signals are transformed in an address transformation to become internal address signals within the semiconductor memory. The internal address is fed to the address decoding circuit instead of the external address signals. The address transformation is processed in such a way that, upon application of a first address with a predetermined address value to the address terminals, a different unit is addressed than when the external address were applied without carrying out the address transformation.

REFERENCES:
patent: 5446692 (1995-08-01), Haraguchi et al.
patent: 5457655 (1995-10-01), Savignac et al.
patent: 5461587 (1995-10-01), Oh
patent: 5493531 (1996-02-01), Pascucci et al.
patent: 5517450 (1996-05-01), Ohsawa
patent: 5544106 (1996-08-01), Koike
"Designing static RAMs for yield as well as speed", Sud et al., Electronics, Jul. 1981, pp. 121-126.

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