Semiconductor memory with bypass circuit

Details Semiconductor memory with bypass circuit Semiconductor memory with bypass circuit

1995-01-23

1995-12-26

Nelms, David C.

Static information storage and retrieval

Read/write circuit

With shift register

365300, 3652257, 365149, 36523005, G11C 1300, G11C 1134

Patent

active

054793700

ABSTRACT:
A semiconductor memory of this invention comprises a memory cell array containing memory cells arranged in matrix form, word lines each connected to all the memory cells in the same row, and bit lines each connected to all the memory cells in the same column, a shift register containing a plurality of stages of shift circuits which is used as a serial address pointer for serially specifying the addresses of actually used rows and/or columns in the memory cell array, a bypass circuit capable of forming a bypass for the shift circuit at a given stage of the shift register, and a bypass control circuit for determining whether or not a bypass is to be formed by the bypass circuit.

REFERENCES:
patent: 4903242 (1990-02-01), Hamaguchi et al.
patent: 4954994 (1990-09-01), Hashimoto
patent: 5005158 (1991-04-01), McClure et al.
patent: 5018110 (1991-05-01), Sugiyama et al.
patent: 5255226 (1993-10-01), Ohno et al.

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