Semiconductor memory with built-in parallel bit test mode

Static information storage and retrieval – Read/write circuit – Testing

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365200, 36523003, 365222, G11C 700

Patent

active

054167418

ABSTRACT:
Disclosed is a semiconductor memory with a built-in test mode which can freely change the width of parallel test bits. This semiconductor memory has pairs of data read/write (RWD) lines commonly provided for each block of a memory cell array laid out as a plurality of blocks, DQ buffers for each amplifying data output on associated pairs of DQ lines from an associated block and sending the amplified data in read mode, and writing data, written on those associated RWD lines, on the associated pairs of DQ lines in write mode. The semiconductor memory further has a test circuit which, in parallel bit test mode, enables those DQ buffers equal or greater in number than those DQ buffers needed for normal reading/writing to connect the associated pairs of RWD lines in wired-OR fashion and read out the results of computation of pieces of data, which are equal to or greater in number than the pairs of RWD lines, onto the pairs of RWD lines in read mode, and to write the same data on those plural pairs of RWD lines equal to or greater in number than the pairs of RWD lines.

REFERENCES:
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patent: 4672582 (1987-06-01), Nishimura et al.
patent: 4873669 (1989-10-01), Furutani et al.
patent: 5265100 (1993-11-01), McClure et al.
patent: 5285419 (1994-02-01), Iyengar
patent: 5301155 (1994-04-01), Wada et al.

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