Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2000-06-30
2002-12-31
Gaffin, Jeffrey (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S023000, C711S105000, C365S145000, C365S203000, C365S210130
Reexamination Certificate
active
06502145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit comprising an interface circuit for receiving and sending data from and to an external device connected to an outside of the semiconductor integrated circuit and a bus for transmitting the data from the interface circuit into the semiconductor integrated circuit, a semiconductor integrated circuit comprising a phase-locked loop (hereinafter referred to as a PLL circuit) for synchronizing an internal clock with an external clock at a high speed, and a semiconductor integrated circuit comprising a DRAM which is small-sized and can easily be tested.
2. Description of the Background Art
In a semiconductor integrated circuit, generally, one chip has a plurality of functions. In other words, a plurality of internal devices having different functions are integrated into the same chip so that the semiconductor integrated circuit is formed.
FIG. 15
is a block diagram showing a structure of a semiconductor integrated circuit which is a so-called one-chip microcomputer. The one-chip microcomputer is also formed with a plurality of internal devices provided on one chip
1
. On the chip
1
is provided a CPU
2
which includes a control circuit for interpreting and executing instructions and serves to perform arithmetic operation. Data such as instructions sent to the CPU
2
are given from internal and external devices provided on the inside and outside of the semiconductor integrated circuit, respectively. The external device is connected to an input-output pin
3
. An interface circuit
4
acting as one of the internal devices is connected to the input-output pin
3
. The interface circuit
4
serves to electrically and functionally match data transfer between the external device connected to the input-output pin
3
and the internal device of the semiconductor integrated circuit. More specifically, the interface circuit
4
controls data transfer on a boundary between the inside and outside of the semiconductor integrated circuit.
In order for the CPU
2
to execute instructions, the semiconductor integrated circuit should fetch data necessary for the CPU
2
. A processing speed of the CPU
2
is limited. Therefore, data generated in the semiconductor integrated circuit and data given from the outside should be held by any internal device until the CPU
2
starts a processing. In order to efficiently transmit data from the internal device such as the CPU
2
to the external device, it is also necessary to hold the data temporarily. In general, a storage is provided in the semiconductor integrated circuit in order to hold data to be processed by the CPU
2
or data waiting to be processed by the CPU
2
and output to the outside. Examples of the storage provided in the semiconductor integrated circuit include a SRAM
5
for sending and receiving data at a maximum speed together with the CPU
2
, a DRAM
6
acting as a main memory for storing large scale data required by the CPU
2
and for holding and storing image data and the like when performing an image processing, and a NVRAM
7
for storing a basic program and data and for storing individual programs necessary for application.
The above-mentioned internal devices include the storage such as the SRAM
5
and the CPU
2
in addition to the interface circuit
4
. In thecase where plural kinds of internal devices other than the interface circuit
4
are provided, the semiconductor integrated circuit can employ an indirect control method in which two or more channels such as a channel for transferring data between the external device and the CPU
2
and a channel for transferring data between the external device and the storage are provided and the interface circuit
4
is caused to switch channels. Furthermore, the semiconductor integrated circuit can also employ a direct control method for directly inputting data from the external device to the CPU
2
and transferring the same data from the CPU
2
to the storage. In the indirect control method, a selector channel and a multiplex channel are used. The selector channel serves to transfer data at a time without breaking a physical connecting relationship between the channel and the interface circuit
4
until data transfer is completed. The multiplex channel serves to transfer data while switching the physical connecting relationship between the channel and the interface circuit
4
on a unit.
Referring to a multi-channel, the interface circuit
4
switches the channels. Therefore, the interface circuit
4
requires information for switching the channels.
In a multi-channel switching method according to the prior art, channels are switched every byte of data or are switched for each block of data by causing the data to have information about channel selection.
Some kinds of data are transmitted. Data which can immediately be executed by the CPU
2
are directly sent to the CPU
2
. Data which should be rewritten to a main memory or stored once are transmitted to a storage side such as the DRAM
6
. As a matter of course, some data should be transmitted to the CPU
2
and the storage at the same time. Some of the data transmitted to the DRAM
6
are used for a cache. Such data are stored in the SRAM
5
simultaneously.
The data to be processed by the CPU
2
and output from the CPU
2
include data to be exactly output to an external device in addition to data to be transferred to the SRAM
5
and the DRAM
6
. In such a case, the prior art can also employ a method for causing the DRAM
6
to store all the data once, connecting the interface circuit
4
to the DRAM
6
by a multiplexer (not shown) and sending only data to be output from the DRAM
6
to the external device. A PLL circuit
8
which is also used in the semiconductor integrated circuit shown in
FIG. 15
will be described below. The PLL circuit
8
is provided to synchronize an internal clock used in the semiconductor integrated circuit with an external clock sent from the outside of the semiconductor integrated circuit. Also in a system chip, the PLL circuit is used. Referring to the system chip, a clock is always set to a power down mode, a refresh mode or the like. Also in such a case, it is important to realize high-speed synchronization in order to increase a speed of operation of the semiconductor integrated circuit performed in response to the internal clock. The internal clock should be synchronized with the external clock to perform communication between the external device and the semiconductor integrated circuit.
As shown in
FIG. 17
, the PLL circuit according to the prior art includes a frequency phase comparator
30
for detecting differences in frequencies and phases, a charge pump
31
for causing a current to flow into or out for a period of time corresponding to a result of the detection performed by the frequency phase comparator
30
, a loop filter
32
for eliminating high-frequency components and noises from an output of the charge pump
31
to obtain a DC voltage, and a ring oscillator
33
for generating an internal clock having a frequency corresponding to an output of the loop filter
32
. In the PLL circuit according to the prior art, one frequency phase comparator performs two processes, that is, a frequency leading-in process for causing frequencies to approximate to each other in order to synchronize the internal clock with the external clock, and a phase synchronizing process for completing phase synchronization.
The semiconductor integrated circuit according to the prior art has the above-mentioned structure. Therefore, input data always arrives at a predetermined destination, and data transfer is terminated while the data cannot be accepted at the destination until the data can be accepted at the same destination. For this reason, it takes a lot of time to transfer the data As shown in
FIG. 15
, for example, data having destination information is sent from the external device to the interface circuit
4
th
Gaffin Jeffrey
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Perveen Rehana
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