Semiconductor memory with a multiplexer for selecting an output

Details Semiconductor memory with a multiplexer for selecting an output Semiconductor memory with a multiplexer for selecting an output

1992-01-31

1993-11-16

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523002, 36523006, 307449, 307463, G11C 1140

Patent

active

052629945

ABSTRACT:
An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder associated with each column, each of which includes a set of address fuses into which an address is programmed, responsive to which its associated redundant column is to be selected. A plurality of redundant sense amplifiers are each associated with a group of redundant columns. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each associated redundant column decoder, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier (or, in a write cycle, its associated write circuit) upon selection of a redundant column. The coupling is accomplished by the redundant multiplexer corresponding to the input/output terminal to which the selected column is associated turning on a pass gate between the redundant sense amplifier (or write circuit) and the input/output circuitry for the input/output terminal.

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patent: 4985866 (1991-01-01), Nakaizumi
Hardee, et al., "A Fault-Tolerant 20 ns/375 mW 16K.times.1 NMOS Static Ram", J. Solid State Circuits, vol. SC-16, No. 5 (IEEE, 1981), pp. 435-443.
Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, vol. SC-19, No. 5 (IEEE, 1984), pp. 545-551.
Sakurai, et al., "A Low Power 46 ns 256 kbit CMOS Static Ram with Dynamic Double Word Line", IEEE J. Solid State Circuits, vol. SC-19, No. 5 (IEEE, Oct. 1984) pp. 578-585.

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