Semiconductor memory with a clock synchronization device...

Details Semiconductor memory with a clock synchronization device... Semiconductor memory with a clock synchronization device...

2003-09-10

2004-07-20

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S211000, C365S194000, C365S233100, C327S362000, C327S378000

Reexamination Certificate

active

06765836

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a synchronization device for a semiconductor memory device, in particular a high-frequency semiconductor memory device or a DDR-RAM memory module. In the synchronization device an input clock signal of the semiconductor memory device can be generated or received and then time-modulated. The time-modulated clock signal can be outputted as an output clock signal and provided to the semiconductor memory device for processing.
In semiconductor memory devices, an operation is based on a clock signal that is externally supplied or internally generated. Memory contents in the semiconductor memory device are stored, read, or deleted according to the clock signal. Because semiconductor devices contain a number of storage units, and a plurality of semiconductor memory units are typically jointly utilized in a circuit configuration—particularly according to a common clock—the synchronicity of the respective clock signals relative to one another and to the outputted data must be taken into consideration for the operation and configuration of modern semiconductor devices, so that each write, read, or delete command can be allocated a corresponding item of data which appears at the semiconductor memory device at a specified time, for example.
These aspects are particularly important in high-frequency or high-cycle semiconductor memory devices and particularly double-data-rate semiconductor memory devices such as DDR-RAMs.
Hitherto, the synchronization requirements have been taken into account by the provision of a synchronization device wherein an input clock signal of the semiconductor memory device can be generated or received, the generated or received input clock signal is time-modulatable, and the time-modulated generated or received input clock signal can be outputted as an output clock signal and made available to the semiconductor memory device for processing.
However, it is problematic that the synchronization device must be tuned to the circuit environment. Hitherto, the tuning has been determined and set in the stationary operating state, i.e. for a specified and predetermined operating temperature of the semiconductor memory device or synchronization device. But when the operating temperature of the semiconductor memory device or synchronization device changes, deviations occur in the tuning of the synchronization behavior of the synchronization device relative to the stationary state. This is particularly disadvantageous for operating from a normal mode into an energy-saving mode, and particularly when moving from the energy-saving mode into the normal mode.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a synchronization device for a semiconductor memory device that overcomes the above-mentioned disadvantages of the prior art devices of this general type, with which a clock signal can be time-tuned in a particularly reliable fashion.
With the foregoing and other objects in view there is provided, in accordance with the invention, a synchronization device for a semiconductor memory device. The synchronization device contains a temperature-controllable delay device for assisting in time modulating an input clock signal. The temperature-controllable delay device receives or generates the input clock signal. The temperature-controllable delay device further generates a signal delay dependent on an operating temperature of the semiconductor memory device. The temperature-controllable delay device outputs an output clock signal based on the input clock signal with a delay equal to the signal delay.
The inventive synchronization device is characterized by the provision of a temperature-controllable or temperature-controlled delay device. Furthermore, a signal delay that is dependent on an operating temperature of the semiconductor memory device can be generated by the temperature-controllable or temperature-controlled delay device. Furthermore, the generated or received clock signal can be outputted by the temperature-controllable or temperature-controlled delay device as an output clock signal with a delay equal to the signal delay.
It is thus a core idea of the present invention to provide a delay device inside the synchronization device that is itself temperature-controllable or temperature-controlled. The temperature-controllable or temperature-controlled delay device generates a signal delay relative to the generated or received input clock signal that takes into account the temperature dependency. The signal delay that is generated according to the respective operating temperature of the semiconductor memory device is taken into consideration in that the generated and received input clock signal is released by the temperature-controlled or temperature-controllable delay device as an output clock signal with a delay equal to the generated signal delay.
The signal delay that is generated as a function of temperature is so selected and set, that the following relation for the input clock signal Cin and the output clock signal Cout can be satisfied, or at least approximately so:
C
out(
t
)=
C
in(
t−&Dgr;t
(&thgr;)).
Here, t is time, &Dgr;t is the signal delay relative to the input clock signals Cin and the output clock signals Cout, and &thgr; is the temperature.
According to the present invention, the temperature-dependent signal delay &Dgr;t(&thgr;) can be generated by the temperature-controlled or temperature-controllable delay device in such a way that the output clock signal Cout or its time characteristic is substantially independent of an operating temperature of the semiconductor memory device.
All the temperature dependencies of the individual portions of particular assemblies that occur in the synchronization device and the semiconductor memory device are taken into account in the overall delay, and the temperature-dependent signal delay &Dgr;t(&thgr;) that is generated by the temperature-controlled or temperature-controllable delay device is adapted so that a signal delay that is constant across all temperatures emerges between the input signal Cin and the output signal Cout for all operating temperatures as a whole for the entire synchronization device and/or for the entire semiconductor memory device including the synchronization device.
In particular, it is provided that a first signal delay &Dgr;t(&thgr;l) and a second signal delay &Dgr;t(&thgr;t
2
) can be generated for each first operating temperature &thgr;
1
and each second operating temperature &thgr;
2
of the semiconductor memory device, respectively, in such a way that the relation
C
out
1
(
t
)=
C
out
2
(
t
)
can be satisfied, or at least approximately so, by the respective output clock signals Cout
1
and Cout
2
at all times t, provided that the relation
C
in
1
(
t
)=
C
in
2
(
t
)
is satisfied by the input signals Cin
1
and Cin
2
, or at least approximately so, at all times t.
What this ultimately results in is that the overall delay between the input clock signal Cin and the output clock signal Cout remains constant, regardless of the operating temperature &thgr;, because the temperature-dependent “additional delay” &Dgr;t(&thgr;) is increased or decreased accordingly.
In particular, it is provided that a relatively shorter signal delay &Dgr;t(&thgr;) is generated given a relatively higher operating temperature &thgr; of the semiconductor memory device.
Alternatively or in addition, it is provided that a relatively long signal delay &Dgr;t(&thgr;) can be generated given a relatively low operating temperature &thgr; of the semiconductor memory device.
It is provided for purposes of performing the temperature-dependent controlling of the signal delay &Dgr;t that a temperature signal T that is representative of the respective operating temperature &thgr; of the semiconductor memory device is or can be utilized, particularly in the form of what is known as a control voltage Vcntrl.
The temperature signal T is advantageously suppliable, namely from outside, by a control li

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