Static information storage and retrieval – Read/write circuit – Testing
Patent
1991-05-09
1992-10-27
Gossage, Glenn
Static information storage and retrieval
Read/write circuit
Testing
365154, 365156, 365226, 365218, 371 211, 371 214, G11C 2900, G11C 514, G11C 11419
Patent
active
051595710
ABSTRACT:
A static random access memory (RAM) includes a data set circuit (DSC) coupled to pairs of load elements of memory cells to test the connection between a pair of load elements and a pair of memory nodes of each of the memory cells. The data set circuit responds to predetermined control signals and data to be set to the memory cells and supplies the predetermined voltage corresponding to such data to the pair of load elements. If the pair of load elements and the memory nodes of a memory cell are properly coupled, data of the memory cell will be inverted. Therefore, if the data of a memory cell is not inverted during the test, it can be quickly determined that a disconnection fault exists at that memory cell location.
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Ito Akira
Ohkuma Tosiyuki
Sato Yoichi
Gossage Glenn
Hitachi , Ltd.
Hitachi VLSI Engineering Corp.
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