Semiconductor memory unit having redundant structure

Details Semiconductor memory unit having redundant structure Semiconductor memory unit having redundant structure

1992-06-16

1994-04-26

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 36523006, G11C 700

Patent

active

053073169

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention generally relates to semiconductor memory devices and, more particularly, to a semiconductor memory device that has a redundancy.
A semiconductor memory device having a redundant construction includes redundant memories in the form of redundant word lines. Such a construction guarantees the normal operation of the memory device as a whole even when a defective memory cell is addressed, by addressing a redundant memory cell in place of the defective memory cell. Such a redundant construction is essential for constructing large scale semiconductor memory devices. In a typical example, the redundant memory cells are provided adjacent to a memory cell array with a number corresponding to two or three word lines. There, a redundant word line is selected when a selected word line contains a defective memory cell. Similarly, the redundant memory cells may be formed in the form of two or three bit lines.
Meanwhile, the large scale semiconductor memory devices having a storage capacity exceeding 4-16 Mbits are generally formed on a chip in the form of a plurality of blocks each having a storage capacity of about 1 Mbits. By doing so, one can reduce the driving power at the time of access. Further, such a construction facilitates a quick selection of the word line or bit line. It should be noted that the parasitic capacitance of the word line or the bit line, caused as a result of a single word line or a single bit line being connected with a large number of memory cells, can be decreased significantly by constructing the device as such. Thereby, the foregoing reduction in the driving power or the reduction in the access time is achieved.


STATE OF THE RELATED ART

FIG. 1 shows a conventional semiconductor memory device that has the redundant construction.
Referring to FIG. 1, the semiconductor memory device includes a memory cell array 10 that includes therein a number of memory cells arranged into a row and column formation, a plurality of word lines WL each connected to the memory cells aligned in a row, a plurality of bit lines BL each connected to the memory cells aligned in a row, a plurality of bit lines BL each connected to the memory cells aligned in a column, a word decoder 13 supplied with address data for selecting a word line, and a sense amplifier/column decoder unit 14 that is supplied with address data for selecting a bit line. In addition, the semiconductor memory device includes a first redundant cell array 11 that is provided adjacent to the memory cell array 10 to extend in the direction of the word lines and a second redundant cell array 12 that is provided also adjacent to the memory cell array 10 to extend in the direction of the bit lines.
As usual, a memory cell that corresponds to the intersection between a selected word line WL and a selected bit line BL is selected in response to the selection of the word line WL and the bit line BL by means of the word decoder 13 and the column decoder 14. In this state, the writing or reading of the data is achieved via the sense amplifier/column decoder 14.
The redundant array 11 includes memory cells, aligned in the row direction, of a number corresponding to two or three word lines. There, the word decoder 13 selects a row of the memory cells that are included in the redundant cell array 11 when the selected word line of the array 10 includes a defective memory cell. Similarly, the redundant array 12 includes memory cells, aligned in the column direction, of a number corresponding to two or three bit lines. The sense amplifier/column decoder 14 selects a column of the memory cells that are included in the redundant cell array 12 when the selected bit line of the array 10 includes a defective memory cell. Further, there is provided a redundancy control circuit 15 on the memory chip in order to control the selection in the redundant cell arrays 11 and 12.
Conventionally, the semiconductor memory device having a storage capacity of about 1 Mbits has been constructed by employing the construction of FIG. 1.

REFERENCES:
patent: 4849939 (1989-07-01), Muranaka et al.
patent: 5033024 (1991-07-01), O'Connell et al.
patent: 5140597 (1992-08-01), Araki

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