Semiconductor memory unit having overlapping addresses

Details Semiconductor memory unit having overlapping addresses Semiconductor memory unit having overlapping addresses

1994-04-29

1995-06-06

Harvey, Jack B.

Static information storage and retrieval

Addressing

Multiple port access

365 63, 36518902, G11C 700

Patent

active

054228573

ABSTRACT:
A memory unit includes a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, and a plurality of write word lines. An array of memory cells are connected to the read bit lines, the read word lines, the write bit lines, and the write word lines. Each of the memory cells includes at least two input sections, at least two output sections, and a memory element. The output sections are connected to at least two of the read word lines, respectively, and output data from the memory element to one of the read bit lines in response to signals on the read word lines. The input sections are connected to at least two of the write word lines, respectively, and output data from one of the write bit lines into the memory element in response to signals on the write word lines. A plurality of decoders connected to the read word lines decode a read address signal into output signals, respectively, which are fed to the read word lines. A plurality of decoders connected to the write word lines decode a write address signal into output signals, respectively, which are fed to the write word lines.

REFERENCES:
patent: 4667310 (1987-05-01), Takada
patent: 4768172 (1988-08-01), Sasaki
patent: 4775942 (1988-10-01), Ferreri et al.
patent: 4791607 (1988-12-01), Igarashi et al.
patent: 4833648 (1989-05-01), Seharrer et al.
patent: 5023844 (1991-06-01), Arnold et al.
Sheldon S. L. Chang, "Multiple-Read Single Write Memory and Its Applications" IEEE Transactions on Computers vol. C.29 No. 8 Aug. 1980.

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