Semiconductor memory unit

Details Semiconductor memory unit Semiconductor memory unit

1988-08-04

1990-06-19

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

36523003, G11C 1134, G11C 700

Patent

active

049358987

ABSTRACT:
A semiconductor memory device having a plurality of memory arrays composed of mutually orthogonal row word lines and complementary column data lines, and static memory cells disposed in a lattice arrangement at the intersections of such word lines and complementary data lines; variable impedance load circuits having first P-channel MOSFETs disposed between the complementary data lines and a first supply voltage and kept normally in an on-state, and also having second P-channel MOSFETs connected in parallel with the first P-channel MOSFETs and cut off selectively in accordance with predetermined selection timing signals in a write mode; a plurality of signal generator circuits provided correspondingly to the memory arrays for forming the selection timing signals in accordance with write control signals and array selection signals, and then feeding the timing signals to the corresponding variable impedance load circuits; and a plurality of signal relay circuits provided correspondingly to a predetermined number of the signal generator circuits in such a manner that each signal relay circuit is disposed substantially at an intermediate position between the corresponding signal generator circuits, and transmitting to the corresponding signal generator circuits the write control signals obtained from the timing generator circuit TG. In this configuration, the signal transmitting paths between the timing generator circuit and the individual signal relay circuits are rendered mutually equivalent in length.

REFERENCES:
patent: 4386419 (1983-05-01), Yamamoto
patent: 4499559 (1985-02-01), Kurafuji
patent: 4760561 (1988-07-01), Yamamoto et al.
S. Miyaoka et al., "A 7ns/350mW 64K EZL Compatible RAM", ISSZC 1987, pp. 132-137, Digest of Technical Papers.
Kobayashi et al., "A 10--.mu.W Standby Power 2,56K CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct., 1985, pp. 935-939.
T. Ohtani et al., "A 25ns 1Mb CMOS SRAM", ISSCC 87, Feb. 27, 1987, pp. 264-265 and 420.
Minato et al., "A 42ns 1Mb CMOS SRAM", ISSCC 87, Feb. 27, 1987, pp. 260-261 and 418.
T. Sakurai et al., "A Low Power 46 ns 256 kbit CMOS Static Ram with Dynamic Double Word Line", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, October, 1984, pp. 578-584.

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