Semiconductor memory unit

Details Semiconductor memory unit Semiconductor memory unit

1993-10-14

1995-09-19

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 3652335, G11C 700

Patent

active

054522528

ABSTRACT:
A semiconductor memory unit that includes a regular memory cell array and a redundant column which utilize common rows for actuating regular memory cells when defective memory cells are detected. A first access device designates a column in the regular memory cell array which corresponds to a externally designated column address. A second access device designates a redundant column which corresponds to the externally designated column address. When the regular memory cell array contains defective memory cells and the column addresses of their cells coincide with the externally designated column address, a validating device validates the access to the redundant column by means of the second access device. When the regular memory cell array contains defective memory cells having column addresses other than that designated externally, the validating device validates the access to the column in the regular memory cell array by means of the first access device.

REFERENCES:
patent: 4754434 (1988-06-01), Wang et al.
patent: 5134583 (1992-07-01), Matsuo et al.
patent: 5146429 (1992-09-01), Kawai et al.
patent: 5197030 (1993-03-01), Akaogi et al.

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