Semiconductor memory testing device and method of testing...

Details Semiconductor memory testing device and method of testing... Semiconductor memory testing device and method of testing...

2011-01-28

2011-11-01

Kerveros, Jame C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S230030

Reexamination Certificate

active

08051344

ABSTRACT:
The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. When the first and second test signals are in an disabled state, the semiconductor memory testing device also includes a plurality of bank control units generating a multi wordline test mode signal as a multi wordline test signal corresponding to a bank control signal, and simultaneously enabling a plurality of wordlines in accordance to the multi wordline test signal to perform a test. The semiconductor memory testing device reduces a testing time and current consumption and thus enhances a more stable voltage drop when performing continuous multi wordline test on a per bank basis.

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USPTO OA mailed Jul. 13, 2010 in connection with U.S. Appl. No. 12/205,036.
USPTO NOA mailed Oct. 29, 2010 in connection with U.S. Appl. No. 12/205,036.

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