Semiconductor memory testing device

Details Semiconductor memory testing device Semiconductor memory testing device

1998-01-26

1999-08-31

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Testing

365200, 371 102, G11C 700

Patent

active

059462477

ABSTRACT:
In a small-size device, one input terminals of a plurality of AND circuits are connected in series. The other terminals of the plurality of AND circuits receive failure information held by a register circuit. Among the AND circuits, by changing values at the AND circuits which are connected in an output direction (i.e., most significant bit side) of an AND circuit receiving a failure bit and values at the AND circuits which are connected in an input direction (i.e., least significant bit side) of the AND circuit receiving the failure bit, a signal line associated with the failure bit is disconnected and signal lines are re-connected to adjacent signal lines including an extra line by selectors. Hence, a failure bit is compensated in a very simple structure.

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