Semiconductor memory testing apparatus

Details Semiconductor memory testing apparatus Semiconductor memory testing apparatus

1999-07-15

2002-12-31

Le, Dieu-Minh (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S718000

Reexamination Certificate

active

06502211

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory testing apparatus that is suitable for testing a semiconductor memory such as a memory constructed by a semiconductor integrated circuit (semiconductor integrated circuit memory; hereinafter referred to as IC memory), and more particularly, to a failure analysis memory for storing therein the test result of a semiconductor memory.
2. Description of the Related Art
FIG. 6
shows a basic configuration of the conventional semiconductor memory testing apparatus of such type. The illustrated semiconductor memory testing apparatus comprises a timing generator
11
, a pattern generator
12
, a waveform formatter
13
, a logical comparator
14
, and a failure analysis memory (FAM)
15
.
The timing generator
11
generates, in order to control the test timing of the entire testing apparatus, a reference clock CLK and various kinds of timing signals (pulses) TS. Although a timing signal TS is applied only to the waveform formatter
13
in
FIG. 6
, it is needless to say that the timing signals are also applied to other units (apparatus, devices and circuits) of the testing apparatus including the logical comparator
14
.
The pattern generator
12
generates, in synchronism with the reference clock CLK supplied from the timing generator
11
, address data ADRD, test pattern data PTND, and control data CNTLD all of which are to be supplied to a semiconductor memory under test (hereinafter referred to as MUT)
16
. These data signals are supplied to the waveform formatter
13
. The waveform formatter
13
converts the inputted data signals, by the timing signals TS supplied from the timing generator
11
, into an address signal ADR, a test pattern signal PTN and a control signal CNTL, respectively, each having a real waveform required for testing. These signals are applied to the MUT
16
.
The write operation and the read-out operation of the MUT
16
are controlled by the control signal CNTL supplied thereto through the waveform formatter
13
, so that a write operation of the test pattern signal PTN applied to the MUT
16
from the waveform formatter
13
and a read-out operation of the written test pattern signal from the MUT
16
can be carried out. The test pattern signal PTN having been written in the MUT
16
is read out therefrom later on, and the read-out response signal RPD is supplied to the logical comparator
14
where the response signal RPD is compared with an expected value signal EXP supplied from the pattern generator
12
to detect whether there is any anticoincidence between both two signals or not, and a decision is rendered that the MUT
16
is defective (failure) or not defective (pass).
The logical comparator
14
determines, when there is any anticoincidence between the two signals, that the memory cell of the MUT
16
at an address thereof from which the response signal RPD has been read out is defective, and generates a failure signal (data) FAIL indicating that fact. Usually, this failure signal FAIL is expressed by a logical “1” signal, and is stored in a memory cell of the failure analysis memory
15
specified by the address signal ADR supplied from the pattern generator
12
. In general, the failure signal (data) is stored in the same address of the failure analysis memory
15
as that of the failure memory cell of the MUT
16
.
On the contrary, when the response signal RPD coincides with the expected value signal EXP, the logical comparator
14
determines that the memory cell of the MUT
16
at an address thereof from which the response signal has been read out is defectless or normal, and generates a pass signal indicating that fact. This pass signal is expressed by a logical “0” signal, and is usually not stored in the failure analysis memory
15
.
After the testing has been completed, a failure analysis for the MUT
16
is carried out with reference to the failure signals FAIL stored in the failure analysis memory
15
. For example, in the case that the failure signals are utilized in carrying out a failure relief of the MUT, a failure map is created based on the read-out failure signals, and a decision is rendered as to whether the relief of the failure memory cells of the MUT
16
can be done or not.
FIG. 7
shows in outline a configuration of the failure analysis memory
15
. The failure analysis memory
15
comprises a memory part
15
A for storing therein a failure signal FAIL, and a control part
15
B for controlling the memory part
15
A such that the memory part
15
A has the same data bit width (the number of bits) and the same word depth as those of the MUT
16
. The control part
15
B comprises an address formatting part
15
B-
1
to which an address signal ADR is inputted from the pattern generator
12
, and a memory control part
15
B-
2
to which a failure signal FAIL is inputted from the logical comparator
14
. Further, although not shown, to a data input terminal of the memory part
15
A is supplied a failure signal FAIL from the logical comparator
14
.
The address formatting part
15
B-
1
formats an address signal ADR supplied from the pattern generator
12
, in accordance with the word structure of the MUT
16
, into a higher order address signal (the most significant bit or several higher order bits including the most significant bit of the address signal ADR) MADR and a lower order address signal (the least significant bit or several lower order bits including the least significant bit od the address signal ADR) LADR separated from each other. The higher order address signal MADR is supplied to the memory control part
15
B-
2
as a signal for controlling an enable signal for a RAM (Random Access Memory) constituting the memory part
15
A, thereby to control the connection of the memory part
15
A in the direction of the word depth. The memory control part
15
B-
2
generates, based on the failure signal FAIL supplied frorn the logical comparator
14
and the higher order address signal MADR supplied from the address formatting part
15
B-
1
, a write control signal WRSG, and supplies it to the memory part
15
A.
The lower order address signal LADR is supplied to the memory part
15
A as an address signal for accessing the memory part
15
A. Accordingly, the addresses of the memory part
15
A are accessed by lower order address signals LADR each supplied from the address formatting part
15
B-
1
.
When both of the lower order address signal LADR supplied from the address formatting part
15
B-
1
and the failure signal FAIL supplied from the logical comparator
14
are logical “1s”, the write control signal WRSG outputted from the memory control part
15
B-
2
becomes effective or valid (logical “1”). As a result, the failure analysis memory
15
writes a logical “1” (corresponding to the generated failure signal FAIL) being applied to the data input terminal of the memory part
15
A in the same address of the memory part
15
A as that of the MUT
16
. After the testing has been completed, the stored contents of the memory part
15
A are read out therefrom, and the analysis of the failure memory cells (addresses) of the MUT
16
is performed. An address of the failure analysis memory
15
from which a logical “1” is read out corresponds to an address of the memory cell of the MUT
16
at which a failure has occurred.
Incidentally, in recent years, a demand for semiconductor memories that can operate at high rate or speed have been increased more and more, and some high-rate operating memories are already in practical use. One of the high-rate operating semiconductor memories includes a memory that operates in burst mode. Burst mode means, in this specification and claims, a mode in which, on the basis of an address signal supplied to a memory, the lower order address bit or bits of this address signal are changed to an address bit or bits (burst address) automatically generated within the memory which is, in turn, accessed by this address bit or bits. By high-rate generation of the burst address in the memory (by generating the burst a

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