Semiconductor memory testing apparatus

Details Semiconductor memory testing apparatus Semiconductor memory testing apparatus

1998-03-18

2000-09-05

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714723, 365201, G11C 2900, G11C 700

Patent

active

06115833&

ABSTRACT:
A semiconductor memory testing apparatus is provided which is capable of storing failure data of many semiconductor memories under test by a small memory capacity. A group of n input terminals IN.sub.1 -IN.sub.n are provided for each of m failure analysis memory units 13.sub.1 -13.sub.m, n being equal to the number of ways n of an interleave operation, and in the low rate test mode, low rate failure data LFAL.sub.1 -LFAL.sub.n are inputted to all the corresponding input terminals IN.sub.1 -IN.sub.n, respectively. Moreover, a plurality of failure format parts FLFO.sub.1 -FLFO.sub.n are provided for the memory control part MCON of each of the m failure analysis memory units, n being equal to the number of ways n of an interleave operation, and low rate failure data LFAL.sub.1 -LFAL.sub.n are stored in n banks BNC#1-BNC#n provided for each memory block MBLK through these n failure format parts FLFO.sub.1 -FLFO.sub.n, respectively.

REFERENCES:
patent: 5363382 (1994-11-01), Tsukakoshi
patent: 5831989 (1998-11-01), Fujisaki
patent: 5841785 (1998-11-01), Suzuki
patent: 5909448 (1999-06-01), Takahashi
patent: 5917833 (1999-06-01), Sato

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