Excavating
Patent
1996-07-18
1998-05-19
Beausoliel, Jr., Robert W.
Excavating
39518301, G01R 3128
Patent
active
057545561
ABSTRACT:
A semiconductor memory manufacturing system including a tester sub-system and a redundancy analysis sub-system. The manufacturing system includes a transfer circuit between the test sub-system and the redundancy analysis sub-system that reduces the number of bits of data transferred to the redundancy analyzer. This speeds up the transfer process and also speeds up the redundancy analysis.
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Citation A, Memory Evaluation Apparatus, Japanese Patent Public Disclosure No. 6498/1987, Katsuhiko Sato, 13 Jan. 1987, pp. 1-2 (English) pp. 617-620 (Japanese).
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Augarten Michael H.
Michaelson Steven A.
Ramseyer Steve G.
Beausoliel, Jr. Robert W.
Iqbal Nadeem
Teradyne, Inc.
Walsh Edmund J.
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