Semiconductor memory test device

Details Semiconductor memory test device Semiconductor memory test device

2007-02-06

2007-02-06

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

10886672

ABSTRACT:
Conventionally, when a burn-in test is performed by means of utilizing a memory BIST circuit, a control of a reset operation for the memory BIST circuit is required from an external source. According to the present invention, it is configured that the memory BIST circuit is used for the burn-in test of a memory macro, and a BIST reset control circuit detects a memory BIST test completion signal from the memory BIST circuit, and automatically resets the memory BIST circuit. Thereby, repetitive continuous tests to the memory macro by the memory BIST circuit can be achieved, and the burn-in test by means of utilizing the memory BIST circuit can be performed.

REFERENCES:
patent: 6834361 (2004-12-01), Abbott
patent: 6981191 (2005-12-01), Dorsey
patent: 6996760 (2006-02-01), Dorsey
patent: 2003/0074617 (2003-04-01), Dorsey
patent: 2003/0074618 (2003-04-01), Dorsey
patent: 2003/0074619 (2003-04-01), Dorsey
patent: 2003/0074620 (2003-04-01), Dorsey
patent: 4296676 (1992-10-01), None
patent: 5196700 (1993-08-01), None
patent: 2000163992 (1998-11-01), None
patent: 117800 (1999-01-01), None
patent: 2003121508 (2003-04-01), None
Japanese Office Action dated Oct. 18, 2005, with English translation.

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