Semiconductor memory test circuit and method for the same

Details Semiconductor memory test circuit and method for the same Semiconductor memory test circuit and method for the same

1999-06-29

2002-05-14

Decady, Albert (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S207000

Reexamination Certificate

active

06389563

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory test circuit and a method for the same. More particularly, it relates to a semiconductor memory test circuit and a method for the same which reduce the test time in testing a semiconductor memory.
2. Description of the Prior Art
Generally, to determine whether cells of a manufactured memory chip are a in Pass state or a in Fail state, assuming that the testing of every one cell is performed in a semiconductor memory, it takes a great deal of time to test a high-integration device, and the test cost increases. Accordingly, a parallel test has been used to reduce the test time.
The parallel test (pt) writes the same data to a plurality of cells and uses an exclusive OR circuit in a reading operation, thereby determining a Pass state “1” when the same data are read by the exclusive OR circuit, or a Pail state “0” when different data is read by the exclusive OR circuit.
A 3RD 64M Extended Data Out Dynamic Random Access Memory (EDO DRAM) performs a parallel test (pt) of 2M×32Bit. For a parallel test of over 2M×32Bit, the 64M EDO DRAM should consider a chip size according to an increase of a read/write data (RWD) line, thus the parallel test over 32Bit is not considered in the 64M EDO DRAM.
Here, unlike a parallel test performing a write/read operation by generally using only two input/output pads, the 3RD 64M EDO DRAM performs, as to a principle of the parallel test, a parallel test by using the same input/output pad as a normal operation as shown in the following TABLE 1, according to each construction.
TABLE 1
NORMAL operation
Parallel Test
X4
I/O 0, 4, 11, 15
I/O 0, 4, 11, 15
X8
I/O 0,2,4,6,9,11,13,15
I/O 0,2,4,6,9,11,13,15
X16
I/O 0-I/O 15
I/O 0-I/O 15
The parallel test is started by enabling a signal “pt” by a WCBR(/WE, /CAS Before /RAS) refresh, and exits by disabling a signal “pt” by CBR(/CAS Before /RAS) refresh or ROR(/RAS only Refresh).
If the signal “pt” is enabled from the WCBR mode, an address combination for driving a cell of 2M×32Bit by the signal “pt” is achieved from a Y-address buffer, has no correlation with each construction (x4/, x8/, x16), and is different in a 4K refresh or an 8K refresh.
In the case of an 8K refresh, the X-address ranges from X0 to X12 because of 8K=2
13
, and addresses (Y8, Y9, Y10, Y11) among a plurality of Y-addresses are compressed by the signal “pt”; thus the Y-address actually driving the Y-decoder ranges from Y0 to Y7.
In the case of a write operation, 32 data per one operation are loaded on a read/write data (RWD) line and are recorded on 32 cells.
In the case of a reading operation, one word line and one Y-input (Yi) per 8M block are enabled in one operation so that data of 4 cells are accessed to a global database (DB) line via 4-bit line pairs and are loaded on 32 RWD lines.
The Pass or Fail state of the data loaded on 32 RWD lines is determined by an exclusive OR circuit positioned to each pad, and the data loaded on 32 RWD lines are output to an I/O pad proper to each construction such as x4/,x8/,x6.
In the case of a 4K refresh, the X-address ranges from X0 to X11 because of 4K=2
12
as well as a previously compressed X12 address, addresses (Y8, Y9, Y10, Y11) among a plurality of Y-addresses are compressed by the signal “pt”, and the following operation is the same as an 8K refresh.
In the parallel test, a write/read operation is achieved through two I/O pads, regardless of each construction such as ×4/, ×8/, ×16, but this 3RD 64M EDO DRAM performs a parallel test through the same I/O pad as the construction. Also, in a reading operation, 32 data are not simultaneously compared by an exclusive OR circuit; only two data belonging to each I/O pad are logically compared by the exclusive OR circuit so that the 3RD 64M EDO DRAM can be tested by writing different data on each I/O pad.
Such a parallel test is shown in the following Table 2.
TABLE 2
4 Mb × 16
8 Mb × 8
16 Mb × 4
8 K
X0-X12
X0-X12
X0-X12
Refresh
(X0-X7:256 Row,
(X0-X7:256 Row,
(X0-X7:256 Row,
X8-X12:256 K
X8-X12:256 K
X8-X12:256 K
Block)
Block)
Block)
Y0-Y8
Y0-Y9
Y0-Y10
(Y0-Y7:256 Yi,
(Y0-Y7:256 Yi,
(Y0-Y7:256 Yi,
Y8-Y9:4 GDB,
Y8-Y9:4 GDB,
Y8-Y9:4 GDB,
Y10-Y11:8 M
Y10-Y11:8 M
Y10-Y11:8 M
Block)
Block)
Block)
4 K
X0-X11
X0-X11
X0-X11
Refresh
(X0-X7:256 Row,
(X0-X7:256 Row,
(X0-X7:256 Row,
X8-X11:256 K
X8-X11:256 K
X8-X11:256 K
Block)
Block)
Block)
Y0-Y9
Y0-Y10
Y0-Y11
(Y0-Y7:256 Yi,
(Y0-Y7:256 Yi,
(Y0-Y7:256 Yi,
Y8-Y9:4 GDB,
Y8-Y9:4 GDB,
Y8-Y9:4 GDB,
Y10-Y11:8 M
Y10-Y11:8 M
Y10-Y11:8 M
Block)
Block)
Block)
The parallel test (pt) such as that in the above Table 2 is made by reducing the number of column addresses in order to drive a manufactured product with ×32Bit. By doubling the activation of a column address, the test speed proportionally doubles.
In the meantime, as the generation of a high-integration semiconductor memory device increases, the number of cells increases four times.
As a result, the test time also increases four times, thereby increasing the test time as well as the test cost.
For example, in case of a 64M DRAM, its test time is about four times of that of a 16M DRAM and 16 times of that of a 4M DRAM, and its test cost is also increased.
Assuming that 128M, 256M, and 1G DRAMs are manufactured in the future, the test time and the test cost will further increase.
In particular, in the case of a long-cycle disturbance test, it takes 64 msec per one cycle in an 8K refresh so that a test time of over 64 msec×8K Row=512sec (i.e., 8 minutes and 32 seconds) is needed.
Also, in the case of a 4K refresh, it takes 64 msec per cycle, so that a test time of over 64 msec×4K Row=256 sec (i.e., 4 minutes and 16 seconds) is needed.
In other words, since a test time of about 4-8 minutes per device is needed, the test time and the test cost will be continually increase in the mass-production of the devices.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor memory test circuit and a method for the same that substantially obviate one or more of the problems due to the limitations and disadvantages of the related art.
It is an objective of the present invention to provide a semiconductor memory test circuit and a method for the same which achieve a new function by using a conventional parallel test signal, and to apply a test time reduction scheme to a long cycle disturbance test in a package test in order to correspond to an increasing test cost as the generation of devices increases in a high-integration semiconductor memory, thereby reducing the test time of a semiconductor memory device.
To achieve the above objective, a semiconductor memory test circuit includes a parallel test circuit for performing a parallel test when inputting a battery backup signal (bbu), a column address signal (cas
5
), a CAS before RAS signal (cbr), a write enable signal (ew), a power-up bar signal (pwrupb), and a row address signal (ras
71
); and a test mode circuit which is controlled by a combination between a parallel test signal (pt) and the battery backup signal (bbu) generated from the parallel test circuit and generates a test time reduction signal (ttrb), whereby the semiconductor memory test circuit compresses one least significant bit indicating a row address of a device in the case of a 4K refresh operation when the test time reduction signal (ttrb) is enabled, and compresses two least significant bits indicating a row address of a device in the case of an 8K refresh operation when the test time reduction signal (ttrb) is enabled.
A semiconductor memory test method includes the step of controlling a test time reduction signal (ttrb) by a combination of a parallel test signal (pt) and a battery backup signal (bbu), wherein the test time reduction signal (ttrb) compresses one least significant bit indicating a row address of a device performing a 4K refresh operation in the case of a 4K refresh operation, and compresses the two least sign

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