Semiconductor memory test apparatus

Details Semiconductor memory test apparatus Semiconductor memory test apparatus

1998-11-10

2000-11-07

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Testing

365191, G11C 700

Patent

active

061445967

ABSTRACT:
A semiconductor memory test apparatus includes a test signal input unit for externally receiving a test word line model signal and a test column address pulse enable signal, which are used for a memory operation in the test mode. The test apparatus also includes a test mode setting unit that receives: a row address strobe bar signal, a column address strobe bar signal, a write enable bar signal and an address signal, and that generates first and second test mode setting signals. A first switching unit switches a signal input from a row address path circuit or from the test signal input unit, in accordance with a first test mode setting signal. A second switching unit switches another signal input from the row address path circuit or from the test signal input unit in accordance with a second test mode setting signal, and outputs the switched signal to the column address path circuit.

REFERENCES:
patent: 5610867 (1997-03-01), DeBrosse et al.
patent: 5777932 (1998-07-01), Chonan
patent: 5793685 (1998-08-01), Suma
patent: 5933379 (1999-08-01), Park et al.

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