Semiconductor memory systems, methods, and devices for...

Details Semiconductor memory systems, methods, and devices for... Semiconductor memory systems, methods, and devices for...

2002-07-19

2004-12-21

Lebentriti, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S148000

Reexamination Certificate

active

06834014

ABSTRACT:

RELATED APPLICATIONS
This application claims the benefit of Korean Patent Application No. 2001-43789, filed Jul. 20, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory systems, and more particularly, to semiconductor memory systems, methods and devices including active termination.
2. Description of the Related Art
Semiconductor memory devices have been widely employed in computer systems such as personal computers or servers. In order to provide higher performance and larger storage capacities in such semiconductor memory devices, memory modules may each include a plurality of semiconductor memory devices, and a plurality of memory modules may be installed in a computer system. A conventional semiconductor memory system may employ a structure where a plurality of memory modules are interconnected in a stub configuration. In a semiconductor memory system having such a stub configuration, a stub series terminated logic (SSTL) standard (in which series resistors are additionally applied to each stub bus structure) may generally be applied when performing bus termination.
FIG. 1
is a circuit diagram of a conventional semiconductor memory system adopting the SSTL standard. Referring to
FIG. 1
, a conventional semiconductor memory system may include data buses
100
,
102
, and
104
, each of the data buses
100
,
102
, and
104
having two ends. One end of data buses
100
and
104
is connected to a termination voltage VTERM through a respective termination resistor RTERM. Memory modules
110
and
120
are arranged between data buses
100
and
102
, and data buses
102
and
104
, respectively, in a stub configuration. In the memory modules
110
and
170
, a series resistor RSTUB is connected to a memory chip, for example, a dynamic random access memory (DRAM)
114
via a data bus
112
.
The structure shown in
FIG. 1
is usually used in double data rate (DDR) DRAMs. A memory system having such a configuration may normally operate at a data rate of about 300 Mbps. However, if the data rate continues to increase, a density of signals may become affected by a stub load. It may thus become difficult to use the memory system of
FIG. 1
at a data rate greater than 500 Mbps. The series resistor RSTUB is introduced to reduce an effect of stub load but may have a limit in improving the performance of the memory system. One way to address this problem may be by using on-chip active termination. In other words, active termination indicates a method wherein termination resistors may be installed in a memory module and a memory controller chip set and wherein the termination resistors are coupled and decoupled as needed. Here, operations of coupling and decoupling the termination resistors can be changed according to the configuration of a memory system and command signals input into the memory system. For example, in the case of controlling termination by changing the configuration of a memory system, termination can be controlled by a memory controller using mode resister settings. On the other hand, when controlling termination with the use of a command signal, it should be determined first which rank of a memory module the command signal input (from the outside the memory module) is applied to. DRAMs in a rank may be unable to determine whether the command signal currently input into a memory system is applied to the rank to which they belong or to other ranks. Accordingly, more terminals for additional control signals may be installed at a memory controller chip set, a memory module connector, and DRAMs (for example, ranks) in each memory module.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, an integrated circuit memory device can be provided for use in a memory system that receives predetermined command/address signals from a memory controller and that reads and writes data in response to the command/address signals. The memory device can include at least one input/output terminal that inputs/outputs data from/to the memory controller via a data input/output bus, at least one termination resistor, and an active termination control signal generator that generates a control signal to control active termination of the at least one data input/output terminal in response to a chip selection signal from the memory controller. At least one switch can be coupled in series with the at least one termination resistor between the at least one input/output terminal and a predetermined voltage. More particularly the at least one switch is switched on/off in response to the control signal such that the at least one input/output terminal is connected/disconnected to/from the predetermined voltage responsive to the control signal and such that the at least one termination resistor is coupled in series between the predetermined voltage and the at least one input/output terminal when the at least one switch is switched on and such that the at least one input/output terminal is decoupled from the predetermined voltage when the at least one switch is switched off.
According to additional embodiments of the present invention, methods can be provided for operating an integrated circuit memory device for use in a memory system that receives predetermined command/address signals from a memory controller and that reads and writes data in response to the command/address signals wherein the integrated circuit memory device comprises at least one input/output terminal that inputs/outputs date from/to the memory controller via a data input/output bus and at least one termination resistor. These methods can include generating a control signal to control active termination of the at least one data input/output terminal in response to a chip selection signal from the memory controller. Responsive to the control signal, the at least one termination resistor can be coupled in series between a predetermined voltage and the at least one input/output terminal, and the at least one termination resistor can be decoupled from between the predetermined voltage and the at least one input/output terminal.


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