Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2010-08-05
2011-11-01
Phan, Trong (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S222000, C365S225700, C365S230030, C365S185090, C365S185110
Reexamination Certificate
active
08050121
ABSTRACT:
A plurality of memory blocks includes real memory cells and redundancy memory cells, are accessed independently during a normal operation mode, and are accessed simultaneously during a test mode in order for common data to be written to the plurality of memory blocks. A block control unit selects the plurality of memory blocks irrespective of a block address signal in order to execute a compression test. During the test mode, a redundancy access unit simultaneously accesses the redundancy memory cells of the plurality of memory blocks when a forced redundancy signal supplied to a block address terminal indicates first level. Therefore, the redundancy memory cells of the plurality of memory blocks may simultaneously access and test without providing any special terminal. As a result, before a defect is relieved, an operation test of the redundancy memory cells may efficiently execute, which may shorten the test time.
REFERENCES:
patent: 5148398 (1992-09-01), Kohno
patent: 5396124 (1995-03-01), Sawada et al.
patent: 5416740 (1995-05-01), Fujita et al.
patent: 5485425 (1996-01-01), Iwai et al.
patent: 5544106 (1996-08-01), Koike
patent: 5652725 (1997-07-01), Suma et al.
patent: 5708612 (1998-01-01), Abe
patent: 5835424 (1998-11-01), Kikukawa et al.
patent: 5970003 (1999-10-01), Miyatake et al.
patent: 6094381 (2000-07-01), Isa
patent: 6388929 (2002-05-01), Shimano et al.
patent: 6459630 (2002-10-01), Nakayama et al.
patent: 6462993 (2002-10-01), Shinozaki
patent: 6496413 (2002-12-01), Taura et al.
patent: 6496428 (2002-12-01), Ohno et al.
patent: 6496429 (2002-12-01), Murai et al.
patent: 6519192 (2003-02-01), Ooishi
patent: 6538924 (2003-03-01), Dono et al.
patent: 6707733 (2004-03-01), Taura et al.
patent: 6894922 (2005-05-01), Hidaka
patent: 6917548 (2005-07-01), Kim et al.
patent: 7088627 (2006-08-01), Bajwa et al.
patent: 7099208 (2006-08-01), Okuyama et al.
patent: 7257020 (2007-08-01), Hidaka
patent: 7281155 (2007-10-01), Eto et al.
patent: 7286431 (2007-10-01), Hidaka
patent: 7379359 (2008-05-01), Sakakibara
patent: 7385863 (2008-06-01), Nishihara et al.
patent: 7821854 (2010-10-01), Kobayashi
patent: 7903482 (2011-03-01), Ozeki
patent: 2006/0044897 (2006-03-01), Maki
patent: 3-22300 (1991-01-01), None
patent: 3-37900 (1991-02-01), None
patent: 3-286498 (1991-12-01), None
patent: 6-243698 (1994-09-01), None
patent: 7-226100 (1995-08-01), None
patent: 2629645 (1997-04-01), None
patent: 2006-73111 (2006-03-01), None
Arent & Fox LLP
Fujitsu Semiconductor Limited
Phan Trong
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