Semiconductor memory system having sense amplifier being activat

Details Semiconductor memory system having sense amplifier being activat Semiconductor memory system having sense amplifier being activat

1994-08-31

1996-04-23

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Differential sensing

365190, 365205, 365233, 365194, 36518908, 365207, 327 52, 327 57, G11C 702

Patent

active

055110312

ABSTRACT:
A memory system is provided wherein array signals begin at the start of a first phase of a system clock and a sense amplifier set signal is developed during a second phase of the system clock which includes an array of memory cells including word lines and bit lines, word drivers connected to the word lines, a word address decoder enabled by the first phase of the clock system and coupled to the word drivers, a bit switch coupling a bit line to a sense amplifier, a system clock inverting circuit, a timing circuit having a first input connected to a late select signal, a second input connected to the inverting circuit and an output connected to the bit switch and a delay circuit having an input coupled to the inverting circuit and an output connected to the sense amplifier.

REFERENCES:
patent: 4339809 (1982-07-01), Stewart
patent: 4435793 (1984-03-01), Oghii
patent: 5058062 (1991-10-01), Wada et al.
patent: 5327394 (1994-07-01), Green et al.

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