Semiconductor memory system having a write control circuit respo

Details Semiconductor memory system having a write control circuit respo Semiconductor memory system having a write control circuit respo

1994-08-31

1996-06-25

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800

Patent

active

055306772

ABSTRACT:
A memory system having a read/write head is provided wherein a system clock or a test clock can be used to initiate a pulse for enabling the read/write head during a write period and a delay circuit coupled to the system clock or to the test clock can be used to terminate the enabling or control pulse, with a write clock having an input coupled to the system clock also used to terminate the enabling or control pulse during a write period.

REFERENCES:
patent: 5031141 (1991-01-01), Guddat et al.
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5204841 (1993-04-01), Chappell et al.
patent: 5235543 (1993-08-01), Rosen
patent: 5258952 (1993-11-01), Coker et al.
patent: 5357479 (1994-10-01), Matsui

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