Semiconductor memory system

Details Semiconductor memory system Semiconductor memory system

1988-10-31

1990-08-21

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365221, 365240, G11C 700

Patent

active

049512536

ABSTRACT:
In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defecting column detection.

REFERENCES:
patent: 4473895 (1984-09-01), Tatematsu
S. Ishimoto et al., "A 256K Dual Port Memory," Feb. 13, 1985, 1985 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 38-39.

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