Semiconductor memory system

Details Semiconductor memory system Semiconductor memory system

2002-05-06

2003-04-15

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S189040

Reexamination Certificate

active

06549469

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory system having a plurality of semiconductor memory devices and a controller for controlling the read and write operation of each semiconductor memory device which are built in.
2. Description of the Related Art
Referring to
FIG. 22
, one example for a conventional semiconductor memory system will be explained.
FIG. 22
is a block diagram schematically showing an arrangement of the conventional semiconductor memory system having a plurality of semiconductor memory devices of which the data read and write operations are controlled by an external CPU. The semiconductor memory system denoted by
90
includes a couple of first and second semiconductor memory devices
91
and
92
which are different from each other in the way for controlling the data read and write operations. The data read and write operations of the semiconductor memory devices
91
and
92
are controlled using commands from an external CPU
99
.
The first semiconductor memory device
91
has a chip select signal input “/S”, an output enable signal input “/OE”, a write enable signal input “/W”, address inputs “A0~Am”, and data I/O ports “DQ1~DQ16”, as the interface ports for CPU
99
. Data reading and writing at high speeds on the first semiconductor memory device
91
is performed using a memory bus between the first semiconductor memory device
91
and the CPU
99
.
The second semiconductor memory device
92
has a chip select signal input “CE#”, an output enable signal input “OE#”, a write enable signal input “WE#”, a reset/power down signal input “RP#”, a write protect signal input “WP#”, address inputs “A0~An”, and data I/O ports “DQ0~DQ15”, as the interface ports for the CPU
99
. Data reading and writing on the second semiconductor memory device
92
is performed by transmitting commands from the address inputs or the data I/O ports.
The CPU
99
has as the interface ports for the memory devices
91
and
92
a chip select signal output “/CSm” which is connected via a control bus
96
to the “/S” port of the first memory device
91
, a chip select signal output “/CSn” which is connected via a control bus
93
a
to the “CE#” port of the second memory device
92
, a read signal output “/RD” which is connected via a control bus
93
b
to the “/OE” port of the first memory device
91
and the “OE#” port of the second memory device
92
, a write signal output “/WR” which is connected via a control bus
93
c
to the “/W” port of the first memory device
91
and the “WE#” port of the second memory device
92
, an I/O port “I/O Port1” which is connected via a control bus
93
d
to the “RP#” port of the second memory device
92
, an I/O port “I/O Port2” which is connected via a control bus
93
e
to the “WP#” port of the second memory device
92
, address outputs “MA0~MAx” which are connected via an address bus
94
to the corresponding “A0~Am” of the first memory device
91
and the “A0~An” of the second memory device
92
, and data I/O ports “D0~D15” which are connected via an data bus
95
to the “DQ1~DQ16” ports of the first device
91
and the “DQ0~DQ15” of the second memory device
92
.
The data read/write operation of the semiconductor memory system will now be explained. The CPU
99
selects either its “/CSm” or “/CSn” port for accessing the first memory device
91
or the second memory device
92
. For accessing the first memory device
91
, the CPU
99
turns its “/CSm” port to L level and selects one of the “A0~Am” port via the address bus
95
. When the “/RD” port is turned to L level, the CPU
99
can read data from the first memory device
91
. On the other hand, when selecting one of the “DQ1~DQ16” ports via the data bus
95
and turning the “/WR” port to L level, the CPU
99
can write data onto the first memory device
91
.
For accessing the second memory device
92
, the CPU
99
drives its two ports “I/O Port 1” and “I/O Port 2” port to turn both the “RP#” and “WP#” ports of the memory device
92
to H level. When the “/CSn” port is turned to L level, the second memory device
92
can be accessed. Then, the CPU
99
releases a read command to the data bus
95
and turns its “/WR” port to L level. At the succeeding cycle, when the “/RD” port is turned to L level with the address bus
94
enabled, the data reading from the second memory device
92
can be carried out. Similarly, the CPU
99
releases a program command to the data bus
95
and turns its “/WR” port to L level. At the succeeding cycle, when the “/WR” port is turned to L level with the address bus
94
and data bus
95
enabled, the data writing onto the second memory device
92
can be carried out.
It is however necessary in the conventional system to write data at two different cycles into the two semiconductor memory devices which are different from each other in the way for controlling the data read/write operation. As the data writing data into each semiconductor memory device is separately carried out, the overall processing operation will be elongated.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide substantially a semiconductor memory system having a plurality of semiconductor memory devices of which the read and write operations can be controlled by commands received from an external CPU, which can minimize the length of time required for reading and writing data on two or more semiconductor memory devices thus increasing the efficiency of data processing.
A semiconductor memory system in one aspect of the present invention includes a first semiconductor memory device, a second semiconductor memory device and a controller.
The first semiconductor memory device has a chip select signal input, an output enable signal input, a write enable signal input, address inputs and data I/O ports, and is arranged so that data reading and writing at high speeds is performed through the interface of the buses connected to the address inputs and the data I/O ports. The second semiconductor memory device has a chip select signal input, an output enable signal input, a write enable signal input, address inputs and data I/O ports, and is arranged so that data reading and writing is controlled by commands provided via the data I/O ports. The controller is arranged responsive to commands from the CPU for controlling the read and write operation of each of the semiconductor memory devices.
In this aspect of the semiconductor memory system, a single write operation of the CPU to the controller can simultaneously write the same data into the semiconductor memory devices. Accordingly, the data writing of the semiconductor memory system can be improved in the efficiency as its consuming time is minimized.


REFERENCES:
patent: 5844843 (1998-12-01), Matsubara et al.
patent: 6034897 (2000-03-01), Estakhri et al.
patent: 6088743 (2000-07-01), Takeda

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