Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2003-01-29
2004-11-30
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S189070, C365S189090
Reexamination Certificate
active
06826087
ABSTRACT:
This application is based on an application No. 2002-25146 filed in Japan, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular relates to techniques for reducing the current consumption of a semiconductor memory device that has a read circuit including a step-up power supply.
2. Prior Art
The following method is typically used to read information from a semiconductor memory device equipped in a microcomputer. One of a plurality of memory cells arranged in the form of a matrix is selected by a word line and a bit line, and stored information is sensed by a sense amplifier from a cell current of the selected memory cell. To supply power to the internal circuitry of such a semiconductor memory device, a step-up power supply that steps up an externally-supplied voltage may be equipped in the semiconductor memory device (e.g. Unexamined Japanese Patent Application Publication No. H10-302492).
FIG. 1
shows a construction of a conventional semiconductor memory device that includes a step-up power supply.
In the drawing, a microcomputer
130
is roughly made up of a CPU
121
which controls the overall microcomputer
130
, and a semiconductor memory device
120
.
The semiconductor memory device
120
includes a step-up power supply
113
, a memory array
7
, word lines
111
, a row decoder
6
, bit lines
112
, a column decoder
8
, a sense amplifier
9
, a data latch
110
, and a pulse generator
5
.
The memory array
7
is made up of a plurality of memory cells which are arranged in the form of a matrix. Each memory cell stores one-bit information.
The word lines
111
are arranged in a Y direction of the memory array
7
.
The row decoder
6
selects one of the word lines
111
using voltage Vg supplied from the step-up power supply
113
and address information AddY given from the CPU
121
.
The bit lines
112
are arranged in an X direction of the memory array
7
.
The column decoder
8
selects one of the bit lines
112
using address information AddX given from the CPU
121
.
The sense amplifier
9
reads one-bit information from a memory cell selected by the row decoder
6
and the column decoder
8
.
The data latch
110
latches the data read by the sense amplifier
9
.
The pulse generator
5
controls the sense amplifier
9
using signals (SLOW and NDS) from the CPU
121
.
The step-up power supply
113
includes a reference voltage generator
1
, a step-up pump
2
, a Vp detector
3
, and a differential amplifier
4
.
The reference voltage generator
1
generates reference voltage VREF.
The step-up pump
2
generates voltage Vp higher than power supply voltage VDD which is supplied from outside.
The Vp detector
3
controls the step-up pump
2
in accordance with comparison between reference voltage VREF generated by the reference voltage generator
1
and voltage Vp generated by the step-up pump
2
.
The differential amplifier
4
generates voltage Vg that is double the level of reference voltage VREF, using voltage Vp.
In such a construction, a read is performed as follows. When address information AddX and AddY are input respectively to the column decoder
8
and the row decoder
6
, the row decoder
6
selects one word line
111
according to address information AddY, whereas the column decoder
8
selects one bit line
112
according to address information AddX. The sense amplifier
9
senses the storage contents of a memory cell selected by the word line
111
and the bit line
112
, and outputs signal DOUT which is high or low depending on the storage contents. The data latch
110
latches DOUT and outputs the data.
When such a read is performed with a long cycle of several microseconds, usually the sense amplifier
9
is activated only while information is being read from the memory array
7
, to reduce current consumption. On the other hand, the step-up power supply
113
constantly generates voltage Vg to guarantee normal read operations.
FIG. 2
shows an operation sequence of the semiconductor memory device
120
, when a read is performed with a long cycle.
At time T
2
, read control signal NDS output from the CPU
121
makes a high to low transition. This causes output SAAV of the pulse generator
5
to transition from low to high. As a result, the sense amplifier
9
which receives SAAV is activated The sense amplifier
9
reads information stored in a selected memory cell, and outputs it as DOUT. At time T
3
, the pulse generator
5
changes SAAV from high to low. At this point, the data latch
110
latches DOUT, and keeps outputting the data until latching in the next cycle. The sense amplifier
9
is deactivated when SAAV becomes low at time T
3
.
In the meantime, voltage Vg is steadily generated by the reference voltage generator land the differential amplifier
4
. On the other hand, voltage Vp generated by the step-up pump
2
has a waveform with some width, since the step-up pump
2
is activated/deactivated by the Vp detector
3
depending on detection of voltage Vp.
When a read is performed with a long cycle, the sense amplifier
9
is activated only while information is actually being read from the memory array
7
, and deactivated once the information has been read and latched. This contributes to a lower current consumption, when compared with the case where the sense amplifier
9
is active during the whole cycle.
Meanwhile, the step-up power supply
113
is active and generates voltage Vg during the whole cycle, as explained earlier. This causes unnecessary current consumption. Given that the step-up power supply
113
consumes a large amount of current, such unnecessary current consumption need be addressed.
SUMMARY OF THE INVENTION
The present invention was conceived in view of the problem described above, and has an object of providing a semiconductor memory device in which the current consumption of a read circuit including a step-up power supply is reduced when compared with conventional semiconductor memory devices.
The stated object can be achieved by a semiconductor memory device having a memory array, including: a read unit operable to read information stored in a memory cell in the memory array; a step-up unit operable to step up a voltage supplied from outside the semiconductor memory device, and supply the stepped-up voltage to the memory cell; a start control unit operable to have the step-up unit start the stepping up after a read cycle begins; a detection unit operable to detect that the stepped-up voltage has reached a predetermined level required for the read unit to read the information from the memory cell, and have the read unit start the reading upon the detection; and a stop control unit operable to have the step-up unit stop the stepping up, when a predetermined time period required for the read unit to complete the reading has elapsed since the detection.
It should be noted here that the step-up unit does not step up the voltage to the predetermined level instantly. Rather, after the start control unit has the step-up unit start the step up, the step-up unit steps up the voltage with time, as a result of which the voltage reaches the predetermined level. The predetermined level here is higher than a power supply voltage supplied from outside, and is a multiple of the reference voltage as one example. The detection by the detection unit is carried out, for example, by comparing a submultiple of the stepped-up voltage (i.e. a voltage obtained by stepping down the stepped-up voltage by means of resistance voltage division) with a constant voltage lower than the power supply voltage.
According to the above construction, the semiconductor memory device starts stepping up the voltage to be supplied to the memory cell, after the read cycle begins. Once the voltage has reached the predetermined level, the actual read operation is launched. The semiconductor memory device stops stepping up the voltage when the predetermined time period has elapsed since the read operation is launched. The pr
Le Vu A.
Matsushita Electric - Industrial Co., Ltd.
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