Semiconductor memory redundant element identification circuit

Details Semiconductor memory redundant element identification circuit Semiconductor memory redundant element identification circuit

1984-04-16

1986-04-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 1300

Patent

active

045861706

ABSTRACT:
A test circuit (10) for a semiconductor memory is provided. The semiconductor memory includes a redundant decoder (70) for receiving memory address signals (66, 68) which is connected to a redundant circuit element via a signal line (72). The redundant decoder (70) can be programmed in accordance with the address of a defective circuit element, such that when the decoder (70) is addressed by the memory address signals (66, 68) the decoder (70) selects a predetermined redundant circuit element. The test circuit (10) generates an output signal (14) indicating that the circuit element selected by the decoder (70) is a redundant circuit element. The output signal (14) is applied to an indicator circuit (16) which is enabled in a test mode by an abnormal condition detector (26). The output (18) of indicator circuit (16) is applied to an external pin (20).

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patent: 4092733 (1978-05-01), Coontz et al.
patent: 4281398 (1981-07-01), McKenny et al.
patent: 4346459 (1982-08-01), Sud et al.

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