Semiconductor memory preventing sense amplifier malfunctions due

Details Semiconductor memory preventing sense amplifier malfunctions due Semiconductor memory preventing sense amplifier malfunctions due

1999-09-09

2000-10-31

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

36518905, 36518904, 365200, G11C 702

Patent

active

061412775

ABSTRACT:
A semiconductor memory includes two memory cores selected, one at a time, to be read from, a data line switch circuit, and a sense amplifier having a pair of input nodes. Each memory core has a memory cell array, a column gate circuit for selectively connecting the bit lines to its associated data line, and a row decoder for selectively driving word lines. At data read time, the data line switch circuit connects the data line of a selected memory core which is to be read from to a predetermined one of the input nodes of the sense amplifier and connects the data line of the non-selected memory core to the other of the input nodes of the sense amplifier. The sense amplifier amplifies the potential difference between its pair of input nodes to thereby sense read data.

REFERENCES:
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patent: 5321655 (1994-06-01), Iwahashi et al.
patent: 5390147 (1995-02-01), Smaeandoiu et al.
patent: 5898614 (1999-04-01), Takeuchi
patent: 6018487 (2000-01-01), Lee et al.
David Hoff et al.; IEEE Journal of Solid-State Circuits, vol. 24, No. 5; "A23-ns 256K EPROM with Double-Layer Metal and Address Transition Detection"; Oct. 1989; pp. 1250-1257.
Kenichi Imamiya et al.; IEEE Journal of Solid-State Circuits, vol. 25, No. 1; "A 68-ns 4Mbit CMOS EPROM with High-Noise-Immunity Design "; Feb. 1990; pp.72-77.

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