Static information storage and retrieval – Powering
Patent
1995-10-05
1996-09-10
Clawson, Jr., Joseph E.
Static information storage and retrieval
Powering
365149, 36518909, 365203, 36523003, G11C 11401
Patent
active
055552153
ABSTRACT:
The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.
REFERENCES:
patent: 4584670 (1986-04-01), Michael
patent: 4896294 (1990-01-01), Shimizu et al.
patent: 4965769 (1990-10-01), Etoh et al.
patent: 4988888 (1991-01-01), Hirose et al.
patent: 5055713 (1991-10-01), Wathnase et al.
patent: 5075577 (1991-12-01), Okitaka
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5079743 (1992-01-01), Suwa et al.
patent: 5083043 (1992-01-01), Yoshida
patent: 5097450 (1992-03-01), Toda et al.
patent: 5140144 (1992-08-01), Okitaka
patent: 5337272 (1994-08-01), Suwa et al.
Tohru Furuyama, et al., "An Experimental 4 Mbit CMOS DRAM", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 4, Oct. 1986, pp. 605-610.
Takashi Ohsawa, et al. "A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5 pp. 663-667.
Katsutaka Kimura, et al., "Power Reduction Techniques in Megabit DRAM's", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 3, Jun. 1986, pp. 381-389.
Syusa Fujii, et al., "A 50-u A Standby 1M.times.1/256K.times.4 CMOS DRAM with High-Speed Sense Amplifier", IEEE Journal of Solid-States, vol. SC-21, No. 5, Oct. 1986, pp. 643-647.
Masakazu Aoki, et al., "A 60-ns 16-Mbit CMOS DRAM with Transposed Data-Line Structure", IEEE Journal of Solid-State, vol. 23, No. 5, Oct. 1988 pp. /1113-9.
Kasumasa Yanagisawa, et al., "A 23-ns IMbit BiCMOS DRAM", ESSCIRC Digest of Technical Papers, Sep. 1989, pp. 184-187.
Isoda Masanori
Itoh Kiyoo
Kume Eiji
Nakagome Yoshinobu
Tanaka Hitoshi
Clawson Jr. Joseph E.
Hitachi Ltd
Hitachi ULSI Engineering Corporation
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