Semiconductor memory operable with low power supply voltage

Details Semiconductor memory operable with low power supply voltage Semiconductor memory operable with low power supply voltage

1996-07-29

1997-12-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Differential sensing

365177, 365208, G11C 702

Patent

active

056943679

ABSTRACT:
A semiconductor memory includes a plurality of first memory cell arrays, a pair of first common data lines which are provided for the plurality of first memory cell arrays, and a sensing section including a pair of first bipolar transistors whose emitters are respectively connected to the first common data lines and first constant current sources. Each first memory cell arrays includes a plurality of second memory cell arrays, a pair of second common data lines, a first differential amplifier including a second constant current source and a pair of second bipolar transistors whose bases are respectively connected to the second common data lines, whose bases are connected to the second constant current source together, and whose collectors are connected to the first common data lines, and a third constant current source of a second differential amplifier. Each second memory cell arrays includes a plurality of third memory cell arrays, a pair of third common data lines, a pair of third bipolar transistors whose bases are respectively connected to the third common data lines, whose emitters are connected to the third constant current source together to constitute the second differential amplifier, and whose collectors are respectively connected to the second common data lines, and a first control circuit for selectively activating the pair of third bipolar transistors. Each third memory cell arrays includes a pair of bit lines, a plurality of memory cells connected to the pair of bit lines, and a second control circuit for selectively connecting the pair of bit lines to the pair of second common data lines.

REFERENCES:
patent: 5331233 (1994-07-01), Urakawa
patent: 5406148 (1995-04-01), Yokomizo
patent: 5550778 (1996-08-01), Takahashi
patent: 5555215 (1996-09-01), Nakagome et al.
"A 6ns ECL 100K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM" IEEE Journal of Solid-State Circuits, vol.27, No.11, Nov. 1992, pp. 15-0-1510.
"A 220-MHz Pipelined 16-Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator" IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994, pp. 1317-1322.

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