Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1994-12-14
1996-09-10
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Data refresh
36518901, G11C 1300
Patent
active
055555276
ABSTRACT:
A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.
REFERENCES:
patent: 4941127 (1990-07-01), Hashimoto
patent: 5485429 (1996-01-01), Ono
Akamatsu Hironori
Fujita Tsutomu
Kotani Hisakazu
Fears Terrell W.
Matsushita Electric - Industrial Co., Ltd.
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