Semiconductor memory, method for controlling refreshment of...

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S230060, C365S229000

Reexamination Certificate

active

06898142

ABSTRACT:
In accordance with the present invention, in order to reduce an averaged consumption current in a stand-by state, there is provided a semiconductor memory device including a memory cell array area which is divided into a plurality of areas, wherein the semiconductor memory device includes: at least one specific area setting unit being electrically coupled to said memory cell array area and adopted to set at least one area defined in said plurality of areas in accordance with an optional criterion; and at least one refresh operation control unit being electrically coupled to said memory cell array area and adopted to perform a refresh operation to the specific area based on at least one kind of specific refresh control signal, which is longer in cycle than a basic refresh control signal at least in a predetermined state of the semiconductor memory device.

REFERENCES:
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patent: 6449204 (2002-09-01), Arimoto et al.
patent: 6501300 (2002-12-01), Hatae
patent: 6751144 (2004-06-01), Takahashi et al.
patent: 4-21992 (1992-01-01), None
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patent: 7-169268 (1995-07-01), None
patent: 2546161 (1996-08-01), None
patent: 11-213658 (1999-08-01), None
patent: 2000-21162 (2000-01-01), None

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