Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-05-31
2002-12-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S230060
Reexamination Certificate
active
06490210
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory integrated circuit, such as DRAMs and, more particularly, to facilitating a burn-in test for a semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness.
2. Description of Related Art
In a large-scale semiconductor memory circuit, a number of signal lines are provided to a memory cell array. For example, a 256 Mbit DRAM includes 128K word lines, 512K pairs of bit lines, and 2K column selecting lines. Among these signal lines, those used for the same purpose are arranged adjacent to each other by using the same wiring layer.
Addresses are assigned to these signal lines in the memory cell array. Generally, a signal line having an odd-numbered address is arranged adjacent to a signal line having an even-numbered address. In a semiconductor memory circuit employing a redundant circuit system, besides a normal memory cell array, a redundant cell array is provided. Addresses are assigned to a plurality of spare signal lines in such a redundant cell array so that an odd-numbered address is adjacent to an even-numbered address, separate from the normal signal lines in the memory cell array.
A redundant cell array is provided so as to be adjacent to a memory cell array, or sandwiched between sub-blocks of a memory cell array. In both the cases, normal signal lines of the memory cell array and spare signal lines of the redundant cell array are not distinguished from each other in the physical layout, but are successively arranged.
Before shipment of a semiconductor memory circuit, a burn-in test is carried out so as to screen out initial failures. A burn-in test often includes applying a voltage between adjacent signal lines so as to carry out an accelerated test of potential short circuits. In this voltage-applying accelerated test, the amount of time required for applying voltage stress between adjacent lines in a number of signal lines, possibly numbering as many as several hundred thousand, is of vital importance. Whether this time can be reduced is a factor in cost-reduction.
If even-numbered addresses and odd-numbered addresses are alternately assigned to signal lines of a DRAM or the like, as mentioned previously, it is possible to simultaneously apply voltage stress between a number of pairs of signal lines adjacent to each other by activating, e.g., the signal lines having the even-numbered addresses. If normal signal lines and spare signal lines are successively arranged, and if the numbers of both the signal lines and the spare lines are even numbers, it is possible to simultaneously apply voltage stress between adjacent lines in the normal signal lines and the spare signal lines by assigning an even-numbered address and an odd-numbered address to each pair of adjacent signal lines.
However, there are cases where there are an odd number of spare signal lines in a redundant cell array. The reason for this is that since the number of spare signal lines is determined by a trade-off between chip size and defect density, sometimes an odd number of lines is selected as the optimum number. In this case, even if it is intended to simultaneously apply voltage stress between adjacent lines of all the normal signal lines and the spare signal lines by selecting all the odd-numbered addresses or all the even-numbered addresses, it is not possible to do it since there may be a portion at a boundary between the normal signal lines and the spare signal lines where both adjacent two signal lines have odd-numbered addresses or even-numbered addresses. In such a case,it is not possible to prevent increases in test time and test costs.
SUMMARY OF THE INVENTION
Given the above-described circumstances, it is an object of the present invention to provide a semiconductor memory integrated circuit which can simultaneously apply voltage stress to all the normal signal lines and spare signal lines to achieve the shortening of test time.
According to a first aspect of the present invention, a semiconductor memory integrated circuit is provided which comprises: a memory cell array in which a plurality of normal signal lines for selecting a memory cell are arranged; a redundant cell array in which three or more odd number spare signal lines for compensating for defectiveness in said memory cell array are arranged; a decoder for decoding an address signal to select a normal signal line; a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line; and a test control circuit for controlling the decoder and the spare decoder to carry out a test of applying a voltage between adjacent lines in the normal signal lines and the spare signal lines, at the time of performing a test, said test control circuit setting potential levels in a signal line group including the normal signal lines and the spare signal lines so that potential levels of two adjacent signal lines are opposite to each other.
In the semiconductor memory integrated circuit of the first aspect according to the present invention, potential levels of two adjacent signal lines in a signal line group including normal signal lines and spare signal lines are set to be opposite to each other. In this way, it is possible to simultaneously apply voltage stress to the normal signal lines and the spare signal lines, thereby reducing the time required for testing a semiconductor memory circuit, and/or the cost involved in carrying out such a test.
According to a second aspect of the present invention, a semiconductor memory integrated circuit is provided which comprises: a memory cell array in which a plurality of normal signal lines for selecting a memory cell are arranged; a redundant cell array in which three or more odd number spare signal lines for compensating for defectiveness in said memory cell array are arranged; a decoder for decoding an address signal to select a normal signal line; a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line; and a test control circuit for controlling the decoder and the spare decoder to carry out a test of applying a voltage between adjacent lines in the normal signal lines and the spare signal lines, at the time of performing a test, said test control circuit assigning addresses to successively arranged signal lines included in a signal line group so that even-numbered addresses and odd-numbered addresses are alternately assigned.
In the semiconductor memory integrated circuit of the second aspect according to the present invention, even-numbered addresses and odd-numbered addresses are alternately assigned to a group of successively arranged signal lines including normal signal lines in a memory cell array and spare signal lines in a redundant cell array. In this way, it is possible to simultaneously apply voltage stress to the normal signal lines and the spare signal lines, thereby reducing the time required for testing a semiconductor memory circuit, and/or the cost involved in carrying out such a test.
REFERENCES:
patent: 5355339 (1994-10-01), Oh et al.
patent: 5383156 (1995-01-01), Komatsu
patent: 5633826 (1997-05-01), Tsukada
patent: 5699307 (1997-12-01), Greason et al.
patent: 6188618 (2001-02-01), Takase
patent: 6301163 (2001-10-01), Hidaka et al.
Nagai Takeshi
Takase Satoru
Banner & Witocoff, Ltd.
Kabushiki Kaisha Toshiba
Le Thong
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