Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2009-10-21
2011-11-22
Phung, Ahn (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S189090, C365S194000
Reexamination Certificate
active
08064241
ABSTRACT:
A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense amplifier determines logics of data read to the bit lines from memory cells in synchronization with the sense amplifier activation signal. An operation of the sense amplifier is started after predetermined amounts of charges are read from the memory cells to the bit lines, that is, after the detection signal is output. Accordingly, even when a timing to output a timing signal becomes early due to a variance of manufacturing conditions of a semiconductor memory, data read from the memory cells can be latched correctly in the sense amplifier. As a result, malfunctions of the semiconductor memory can be prevented.
REFERENCES:
patent: 5357468 (1994-10-01), Satani et al.
patent: 6661697 (2003-12-01), Yamamoto et al.
patent: 6836426 (2004-12-01), Fukushi et al.
patent: 2002/0080670 (2002-06-01), Kawasumi
patent: 2003/0202412 (2003-10-01), Nii et al.
patent: 2004/0062115 (2004-04-01), Takeuchi et al.
patent: 2004/0183508 (2004-09-01), Toyoda et al.
patent: 2005/0195639 (2005-09-01), Fukushi et al.
patent: 2005/0207239 (2005-09-01), Kodama
patent: 2006/0023485 (2006-02-01), Yamamura
patent: 2008/0247227 (2008-10-01), Tonomura et al.
patent: 07-050094 (1995-02-01), None
patent: 09-231771 (1997-09-01), None
patent: 11-203873 (1999-07-01), None
patent: 2002-133857 (2002-05-01), None
patent: 2002-260386 (2002-09-01), None
patent: 2003-323792 (2003-11-01), None
patent: 2005-129151 (2005-05-01), None
patent: 2006-31798 (2006-02-01), None
International Search Report of PCT/JP2007/000533. mailing date of Feb. 26, 2008.
Shoichiro Kawashima, et al, “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM”, Journal of Solid-State Circuits, May 2002, pp. 592-597, vol. 37, No. 5.
Notification Concerning Transmittal of Translation of International Preliminary Report on Patentability (Form PCT/IB/326) of International Application No. PCT/JP2007/000533 mailed Dec. 3, 2009 with Forms PCT/IB/373, PCT/ISA/237 and PCT/IB/338.
Supplementary European Search Report mailed Jun. 29, 2011 for corresponding European Application No. EP 07 73 7189.
Morita Keizo
Nakabayashi Ken-ichi
Fujitsu Patent Center
Fujitsu Semiconductor Limited
Nguyen Hein
Phung Ahn
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