Semiconductor memory including static random access memory...

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S230050, C365S177000

Reexamination Certificate

active

06977837

ABSTRACT:
A semiconductor memory is formed of first, second, third, fourth, fifth and sixth field effect transistors. The first and second transistors have a first line as gates, one ends of current paths of the first and second transistors are connected to a reference potential electrode. The third and fourth transistors have a second line as gates, and one ends of current paths of the third and fourth transistors are connected to the reference electrode. The fifth transistor has a first word line as a gate, and one end of a current path of the fifth transistor is connected to the other ends of the current paths of the first and second transistors. The sixth transistor having a second word line as a gate, and one end of a current path of the sixth transistor is connected to the other ends of the current paths of the third and fourth transistors.

REFERENCES:
patent: 4709352 (1987-11-01), Kitazawa
patent: 5287301 (1994-02-01), Redgrave
patent: 5726936 (1998-03-01), Whitfield
patent: 6181608 (2001-01-01), Keshavarzi et al.
patent: 2004/0223375 (2004-11-01), Annavajjhala
patent: 2-263473 (1990-10-01), None
E. J. Nowak, et al., “A Functional FinFET-DGCMOS SRAM Cell”, IEDM Technical Digest, International Electron Devices meeting 2002, pp. 411-414, 2002.

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