Semiconductor memory including means for noise suppression

Details Semiconductor memory including means for noise suppression Semiconductor memory including means for noise suppression

1985-11-25

1990-07-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Noise suppression

365149, 365210, G11C 1300

Patent

active

049439499

ABSTRACT:
A half precharge type dynamic RAM has a pair of data lines to which a plurality of dynamic memory cells are coupled. The paired data lines are set in advance before a read operation at a reference potential which is equal to one half of the supply voltage. One of the paired data lines is switched to have a higher or lower level than the reference potential by the memory cell selected. The potential difference applied between the paired data lines is amplified by the operation of a sense amplifier. Here, an address selecting MOSFET in the memory cell has a gate capacitance which will undesirably couple a word line and the data lines. As a result, one of the data lines has its level changed in an undesired manner. The noise inparted between the paired data lines by such coupling noise components can be substantially neglected by adopting a dummy MOSFET which operates to impart coupling noise components corresponding to the noise components caused by the address selecting MOSFET gate capacitance.

REFERENCES:
patent: 4551820 (1985-11-01), Matsuura
patent: 4602355 (1986-07-01), Watanabe
patent: 4719597 (1988-01-01), Kumanoya et al.

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