Semiconductor memory including cell(s) with both charge...

Details Semiconductor memory including cell(s) with both charge... Semiconductor memory including cell(s) with both charge...

2002-03-28

2004-04-27

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S304000, C257S305000, C257S320000, C257S321000

Reexamination Certificate

active

06727544

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
This application is related to Japanese Patent Application No. 2001-142454 filed on Mar. 30, 2001, No. 2001-264927 filed on Jun. 23, 2001, No. 2001-264928 filed on Jun. 23, 2001, No. 2001-266490 filed on Jun. 23, 2001 and No. 2001-266491 filed on Jun. 23, 2001, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and its production process, and more particularly, the invention relates to a semiconductor memory provided with a memory transistor having a charge storage layer and a control gate, and its production process.
2. Description of Related Art
As a memory cell of an EEPROM, is known a device of a MOS transistor structure having a charge storage layer and a control gate in a gate portion, in which an electric charge is injected into and released from the charge storage layer by use of a tunnel current. In this memory cell, data “0” and “1” are stored as changes in a threshold voltage by the state of the charge in the charge storage layer. For example, in the case of an n-channel memory cell using a floating gate as the charge storage layer, when a source/drain diffusion layer and a substrate are grounded and a high positive voltage is applied to the control gate, electrons are injected from the substrate into the floating gate by a tunnel current. This injection of electrons shifts the threshold voltage of the memory cell toward positive. When the control gate is grounded and a high positive voltage is applied to the source/drain diffusion layer or the substrate, electrons are released from the floating gate to the substrate by the tunnel current. This release of electrons shifts the threshold voltage of the memory cell toward negative.
In the above-described operation, a relationship of capacity coupling between the floating gate and the control gate with capacity coupling between the floating gate and the substrate plays an important role in effective injection and release of electrons, i.e., effective writing and erasure. That is, the larger the capacity between the floating gate and the control gate, the more effectively the potential of the control gate can be transmitted to the floating gate and the easier the writing and erasure become.
With recent development in semiconductor technology, especially, in micro-patterning techniques, the size reduction and the capacity increase of memory cells of EEPROM are rapidly progressing. Accordingly, it is important how large capacity can be ensured between the floating gate and the control gate.
For increasing the capacity between the floating gate and the control gate, it is necessary to thin a gate insulating film therebetween, to increase the dielectric constant of the gate insulating film or to enlarge an area where the floating gate opposes the control gate.
However, the thinning of the gate insulating film is limited in view of reliability of memory cells. For increasing the dielectric constant of the gate insulating film, a silicon nitride film is used as the gate insulating film instead of a silicon oxide film. This is also questionable in view of reliability and is not practical.
Therefore, in order to ensure a sufficient capacity between the floating gate and the control gate, it is necessary to set a sufficient overlap area therebetween. This is, however, contradictory to the size reduction of memory cells and the capacity increase of EEPROM.
In an EEPROM disclosed by Japanese Patent No. 2877462, memory transistors are formed by use of sidewalls of a plurality of pillar-form semiconductor layers arranged in matrix on a semiconductor substrate, the pillar-form semiconductor layers being separated by trenches in a lattice form. A memory transistor is composed of a drain diffusion layer formed on the top of each pillar-form semiconductor layer, a common source diffusion layer formed at the bottom of the trenches, and a charge storage layer and a control gate which are around all the periphery of the sidewall of the pillar-form semiconductor layer. The control gate is provided continuously for a plurality of pillar-form semiconductor layers lined in one direction so as to form a control gate line, and a bit line is connected to drain diffusion layers of a plurality of memory transistors lined in a direction crossing the control gate line. The above-described charge storage layer and the control gate are formed in a lower part of the pillar-form semiconductor layer. In a one transistor/one cell structure, if a memory transistor is over-erased, i.e., a reading potential is 0 V and the threshold is negative, a cell current flows in the memory cell even if it is not selected. To surely prevent this inconvenience, a selection gate transistor is provided above the memory transistor. The selection gate transistor has a gate electrode formed to surround at least a part of the periphery of the pillar-form island semiconductor layer in an upper part of the pillar-form semiconductor layer.
The prior-art EEPROM memory cell has the charge storage layer and the control gate which are formed by use of the sidewall of the island-like semiconductor layer to surround the pillar-form semiconductor layer. With this construction, a sufficiently large capacity can be ensured between the charge storage layer and the control gate with a small area occupied. The drain regions of the memory cells connected to the bit lines are formed on the top of the pillar-form semiconductor layers and completely insulated from each other by the trenches. A device isolation region can further be decreased and the memory cells are reduced in size. Accordingly, it is possible to obtain a mass-storage EEPROM with memory cells which provide excellent writing and erasing efficiency.
Hereinafter, explanation is given of a prior-art EEPROM with reference to figures.
FIG. 1651
is a plan view of the prior-art EEPROM, and FIGS.
1652
(
a
) and
1652
(
b
) are sectional views taken on lines A-A′ and B-B′, respectively, in FIG.
1651
.
In
FIG. 1651
, pillar-form silicon semiconductor layers
2
are columnar, that is, the top thereof is circular. However, the shape of the pillar-form silicon semiconductor layers need not be columnar. In the plan view of
FIG. 1651
, selection gate lines formed by continuing the gate electrodes of the selection gate transistors are not shown for avoiding complexity of the figure.
In the prior art, is used a P-type silicon substrate
1
, on which a plurality of pillar-form P-type silicon layers
2
are arranged in matrix. The pillar-form P-type silicon layers
2
are separated by trenches
3
in a lattice form and functions as memory cell regions. Drain diffusion layers
10
are formed on the top of the silicon layers
2
, common source diffusion layers
9
are formed at the bottom of the trenches
3
, and oxide films
4
are buried at the bottom of the trenches
3
. Floating gates
6
are formed in a lower part of the pillar-form silicon layers
2
with intervention of tunnel oxide films
5
so as to surround the pillar-form silicon layers
2
. Outside the floating gates
6
, control gates
8
are formed with intervention of interlayer insulating films
7
. Thus memory transistors are formed. Here, as shown in FIGS.
1651
and
1652
(
b
), the control gates
8
are provided continuously for a plurality of memory cells in one direction so as to form control gate lines (CG
1
, CG
2
, . . . ). Gate electrodes
32
are provided around an upper part of the pillar-form silicon layers
2
with intervention of gate oxide films
31
to form the selection gate transistors, like the memory transistors. The gate electrodes
32
of the selection gate transistors, like the control gates
8
of the memory cells, are provided continuously in the same direction as that of the control gates
8
of the memory cells so as to form selection gate lines, i.e., word lines WL (WL
1
, WL
2
, . . . ).
Thus, the memory transistors and the sel

Affiliated with

Also associated with

Rating

Semiconductor memory including cell(s) with both charge... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory including cell(s) with both charge..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory including cell(s) with both charge... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3201765