Semiconductor memory in which error correction is performed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S774000

Reexamination Certificate

active

07610542

ABSTRACT:
A synchronous semiconductor memory which performs a pipeline operation includes an error correction circuit, an output circuit, and first and second write circuits. The first write circuit is configured to overwrite at least a portion of externally input write data on data read out from a memory cell and corrected by the error correction circuit, and write the overwritten data in the memory cell. The output circuit is configured to output the overwritten data outside a chip. The second write circuit is configured to reoverwrite at least a portion of write data which is externally input at a different time on the overwritten data, encode the reoverwritten data, and write the encoded data in the memory cell.

REFERENCES:
patent: 6701480 (2004-03-01), Karpuszka et al.
patent: 7275200 (2007-09-01), Leung
patent: 7328365 (2008-02-01), Karpuszka et al.
patent: 7353438 (2008-04-01), Leung et al.
patent: 7392456 (2008-06-01), Leung et al.
patent: 7464320 (2008-12-01), Nagai et al.
patent: 4-349549 (1992-12-01), None
Ken Gray, “Adding Error-Correcting Circuitry to ASIC Memory”, IEEE Spectrum, Apr. 2000, pp. 55-60.

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