Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-06-16
2009-10-27
Baker, Stephen M (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S774000
Reexamination Certificate
active
07610542
ABSTRACT:
A synchronous semiconductor memory which performs a pipeline operation includes an error correction circuit, an output circuit, and first and second write circuits. The first write circuit is configured to overwrite at least a portion of externally input write data on data read out from a memory cell and corrected by the error correction circuit, and write the overwritten data in the memory cell. The output circuit is configured to output the overwritten data outside a chip. The second write circuit is configured to reoverwrite at least a portion of write data which is externally input at a different time on the overwritten data, encode the reoverwritten data, and write the encoded data in the memory cell.
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Baker Stephen M
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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