Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-09-21
2004-04-13
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C327S276000, C365S222000
Reexamination Certificate
active
06721910
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to semiconductor memory devices and methods for testing semiconductor memory devices. More particularly, the present invention relates to a method for testing semiconductor memory devices, which are operated by acquiring external commands and external addresses synchronously with high frequency clock signals.
In recent synchronous dynamic random access memories (SDRAM), the cycle time (RAS cycle time) for acquiring external commands has been reduced to 60 nanoseconds. Such SDRAMs acquire external command signals in synchronism with clock signals and are operated at high speeds. More specifically, the conventional SDRAM acquires a row address simultaneously with an active command during a read/write operation. The SDRAM then acquires a column address simultaneously with an active command.
Since the recent SDRAMs use control signals (i.e., bit wire short signals, word wire latch signals, and sense amplifier latch signals) having shortened cycles, the transmission timing of the control signals must be accurate. Thus, the timing of the control signals is adjusted by employing an electron-beam (EB) tester to perform a focused ion beam (FIB) process.
The SDRAM undergoes various testing. For example, an internal refresh counter test is carried out on the SDRAM in accordance with the following procedures. First, when entering a counter test cycle in response to a test command, the row address indicated by the count value of the internal counter is accessed. This increments the value of the internal refresh counter. Test data is then written at a predetermined column address in response to a write command. The SDRAM then exits the counter test cycle. Afterward, the counter test cycle is entered again in response to a test command. After the value of the internal refresh counter is incremented, predetermined data is written on the incremented column address by another write command.
The write process is performed repeatedly thereafter. When the count value of the internal refresh counter reaches a final value, the executed command is changed from the write command to a read command and a data check is carried out. The command is shifted when re-entering the test mode after exiting the test mode.
Generally, when the SDRAM is in the test mode, a so-called write-read process, in which test data is immediately read after the test data is written, is also performed to test every cell.
A RAM which acquires commands in short cycles of 20 nanoseconds has also been proposed. The FCRAM is adapted to cope with high speeds by acquiring external commands (read/write command) and external addresses (row address and column address) in synchronism with clock signals. Such a RAM is referred to as a fast cycle (FC) RAM. The control signals of the FCRAM have cycles that are shorter than those of the SDRAM described above. Furthermore, the FCRAM differs from the conventional SDRAMs in that active commands are not used. The FCRAM is provided with an auto precharge function which automatically executes precharge after the read process or the write process to increase the speed.
The FCRAM operates at a higher speed than the SDRAM. Thus, when the technology applied to the SDRAM is applied to the DRAM, the following shortcomings occur.
(1) Due to the FCRAM's control signal cycle, which is shorter than the SDRAM's control signal cycle, the FCRAM cannot adjust the timing as accurately as the SDRAM if the timing is adjusted in the same manner as the SDRAM. More particularly, the FIB process carried out on the SDRAM is performed before a protective film, such as polyimide, is applied to the circuits of the device since the timing cannot be adjusted unless the wires are uncovered. However, the protective film greatly affects the wire capacitance and changes the delay times of the control signals. Thus, the formation of the protective film varies the timing even if the timing is adjusted through the FIB process. Accordingly, the timing cannot be adjusted with high accuracy regardless of whether the timing adjustment is carried out before the formation of the protective film. That is, the timing cannot be adjusted if the protective film is applied as in the actual state of usage.
(2) The FCRAM acquires the row addresses and column addresses simultaneously and activates the RAS and CAS circuits simultaneously. Therefore, when the FCRAM carries out the same counter test as the SDRAM, the refresh counter value is incremented whenever entering the test cycle in accordance with the test command. Furthermore, since the FCRAM acquires the row address and the column address simultaneously, the value of the refresh counter is incremented each time the write command is acquired. This writes test data on every other cell. Thus, every cell cannot be tested if the read/write operation is performed in the same manner as the SDRAM.
(3) The performance of a burn-in test on the FCRAM to effectively eliminate initial malfunctions also leads to a shortcoming. The burn-in test is carried out to detect initial malfunctions by actuating the device under conditions that are higher than the rated ambient temperature and the rated power supply voltage.
During the burn-in test, the device may be operated with an extremely long cycle of several hundreds of microseconds. In such case, the FCRAM automatically performs precharge after a read process or a write process regardless of the clock cycle. Thus, the FCRAM is in a precharge state during most of the test time. Accordingly, the FCRAM cannot be tested effectively.
Furthermore, the auto precharge is performed each time the refresh counter is operated when performing the counter test. Accordingly, the precharge operation is not necessary when testing only the refresh counter.
Accordingly, it is an objective of the present invention to provide a semiconductor memory device which performs tests efficiently and with high accuracy.
SUMMARY OF THE INVENTION
To achieve the above objective, the present invention provides a method for testing a semiconductor memory device that acquires an external command and an external address in synchronism with a clock signal. The device includes a signal wire through which a control signal is provided and a plurality of capacitors connected in parallel to the signal wire via a plurality of switch circuits. The method includes the steps of connecting a predetermined number of the capacitors to the signal wire by making a predetermined number of the switch circuits conductive, providing the control signal to the signal wire, measuring the transmission time of the control signal, and varying the capacitance of the signal wire by altering the number of the conductive switch circuits.
In a second aspect of the present invention, a semiconductor memory device that acquires an external command and an external address simultaneously in synchronism with a clock signal is provided. The device includes a signal wire through which a control signal is provided, a plurality of capacitors connected in parallel to the signal wire via a plurality of switch circuits, a test mode setting circuit for generating a mode signal provided to the signal wire in accordance with the external command, and a selecting circuit connected to the test mode setting circuit and each of the switch circuits for generating a selection signal, which selects the switch circuit that is made conductive, and provides the selection signal to the selected switch circuit when receiving the mode signal from the test mode setting circuit.
In a third aspect of the present invention, a method for testing a semiconductor memory device that acquires an external command and an external address in synchronism with a clock signal is provided. The device includes a refresh counter for generating an internal address, and an address latch circuit for latching either the external address or the internal address. The method includes the steps of providing a mode signal which instructs the device to execute operations and providing a
Fujioka Shin-ya
Ninomiya Kazuhiro
Sato Yasuharu
Arent & Fox PLLC
Fujitsu Limited
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