Semiconductor memory having variable memory size and method...

Details Semiconductor memory having variable memory size and method... Semiconductor memory having variable memory size and method...

2006-08-22

2006-08-22

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S236000, C365S239000

Reexamination Certificate

active

07095670

ABSTRACT:
A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods. An address sorting circuit receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block. The word lines of the memory array are refreshed according to the second multi-bit address signal.

REFERENCES:
patent: 5890198 (1999-03-01), Pawlowski
patent: 6137743 (2000-10-01), Kim
patent: 6570801 (2003-05-01), Yoshida et al.
patent: 6754126 (2004-06-01), Yamaguchi et al.
patent: 100276386 (2000-09-01), None

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