Semiconductor memory having transistors connected in series

Details Semiconductor memory having transistors connected in series Semiconductor memory having transistors connected in series

2000-07-13

2002-06-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185120, C365S185240

Reexamination Certificate

active

06411548

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-198978, filed Jul. 13, 1999; and No. 2000-208341, filed Jul. 10, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
(1) Background 1
The present invention relates to a semiconductor memory and, more particularly, to an Ferroelectric Random Access Memory (Ferroelectric RAM).
An Ferroelectric RAM is a semiconductor memory that uses a ferroelectric film as part of a memory cell. The polarization state of this ferroelectric film determines the data (“0”or “1”) in the memory cell. The Ferroelectric RAM has many characteristic features, e.g., capabilities of performing high-speed operation, reducing power consumption, increasing memory capacity, and increasing the allowable number of re-write operations (write/erase cycles), and nonvolatility, i.e., retaining data in the absence of power.
Presently, as memory cells for the Ferroelectric RAM, a memory cell obtained by replacing the capacitor insulating film of a memory cell for a DRAM (Dynamic Random Access Memory) with a ferroelectric film, a memory cell obtained by replacing the gate insulating film of a MISFET (Metal Insulated Semiconductor Field Effect Transistor) with a ferroelectric film, and the like are known.
A memory cell having a structure obtained by replacing the gate insulating film of a MISFET with a ferroelectric film is called an MFSFET (Metal-Ferroelectric-Semiconductor Field Effect Transistor). The MFSFET implements a memory function by controlling a current flowing between the source region and the drain region in accordance with the polarization state of the ferroelectric film (assume that polarization which is positive on the substrate side and negative on the gate electrode side is under-direction polarization, and polarization which is negative on the substrate side and positive on the gate electrode side is upper-direction polarization).
In comparison with a memory cell obtained by replacing the capacitor insulating film of a DRAM with a ferroelectric film, an MFSFET allows a reduction in cell size based on the scaling law, and hence suited to achieving an increase in memory capacity and a reduction in chip area. In addition, the MFSFET has an excellent feature that it allows nondestructive data read operation. On the other hand, the MFSFET has its unique technical problems for practical use, e.g., a problem in the process of forming a ferroelectric film on a semiconductor substrate (silicon substrate) (interdiffusion of atoms or the relative dielectric constant of a buffer layer when it is used).
For example, the following are presently known as research papers on the Ferroelectric RAM having MFSFETs:
reference 1: H. Ishihara et al., “Proposal of a Single-Transistor-Cell-Type Ferroelectric Memory Using an SOI structure and Experimental Study on the Interference Problem in the Write Operation”
Jpn J. Appl. Phys. Vol.
36, pp. 1655-1658, Mar. 1997,
reference 2: Hiroshi Ishihara, “Fabrication of ferroelectric-gate FETs and their application to neural networks”
OYO BUTURI
, Vol. 66, No. 12, pp. 1335-1339 (1997), and
reference 3: Hiroshi Ishihara, “Current state of Ferroelectric-gate FETs and their problems”, Technical Report of IEICE ED97-213, pp. 9-16, Mar. 1998.
A prototype technique for the current MFSFETs is disclosed in the patent application filed by Bell Telephone Laboratories (W. L. Brown, U.S. Pat. No. 2,791,759, I. M. Ross, U.S. Pat. No. 2,791,760) in 1955.
Ever since the proposal of this technique, research and development on MFSFETs have been intermittently conducted over 40-odd years. With regard to MFSFETs, however, unique technical problems which are difficult to solve, the challenge of obtaining excellent interface characteristics by preventing interdiffusion of atoms between a ferroelectric film and a semiconductor film (silicon film), in particular, have not been satisfactorily solved. Currently, therefore, MFSFETs have not reached a level at which they can be put into practical use.
Recently, in order to cope with increases in speed and complexity of electronic devices, there have been strong user demands for semiconductor memories which can realize faster operation, over power consumption, larger memory capacity, a larger allowable number of re-write operations, nonvolatility, and the like. Under the circumstances, a great deal of attention has been paid to the Ferroelectric RAM which can meet such demands, and research and development on the Ferroelectric RAM having MFSFETs have been vigorously conducted mainly in Japan and Korea.
A prototype of an Ferroelectric RAM has a so-called simple matrix structure in which stripe electrodes extending in the Y-direction are arranged below a ferroelectric film, and stripe electrodes extending in the X-direction are arranged on the ferroelectric film. In this structure, however, in program operation, a voltage is partly applied to unselected cells other than a selected cell. For this reason, repetitive write operation causes an interference effect, i.e., inversion of the data an unselected cells.
In order to prevent this interference effect, therefore, research and development have currently been conducted on an Ferroelectric RAM having an active matrix structure using FETs for cell selection, an Ferroelectric RAM as an improvement of an Ferroelectric RAM having a simple matrix structure, and the like.
FIG. 1
shows an embodiment of the conventional cell array arrangement of an Ferroelectric RAM using MFSFETs.
FIG. 2
is an equivalent circuit of the device in FIG.
1
.
This Ferroelectric RAM is disclosed in reference
3
and has a simple matrix structure.
A silicon oxide film (SiO
2
)
12
is formed on a silicon substrate
11
. For example, striped silicon films
13
extending in the Y-direction are formed on the silicon oxide film
12
. Each silicon film
13
has a p-type region and two n-type regions sandwiching the p-type region. The silicon substrate
11
, silicon oxide film
12
, and silicon film
13
constitute an SOI (Silicon On Insulator) structure.
Ferroelectric films
14
are formed on the silicon films
13
to completely cover the silicon films
13
.
Striped metal films (gate electrodes)
15
extending in the X-direction are formed on the ferroelectric films
14
. The silicon films (silicon stripes)
13
and metal films (metal stripes)
15
are arranged to intersect at right angles, thereby forming a simple matrix structure. MFSFETs
16
are formed at the intersections of the silicon films
13
and metal films
15
.
In the cell array structure, plural memory cells formed in one silicon stripe are connected in parallel with each other and share one source region and one drain region. For this reason, there is no need to form contact holes for the source and drain regions in each memory cell, and hence this structure is suited to increasing the packing density of memory cells.
The basic operation of the Ferroelectric RAM shown in
FIGS. 1 and 2
will be described next.
For the sake of descriptive convenience, assume that in the following description, an electric field generated in the ferroelectric film when a low potential is applied to the silicon film
13
and a high potential is applied to the metal film
15
is defined as an under-direction electric field, and an electric field generated in the ferroelectric film when a high potential is applied to the silicon film
13
, and a low potential is applied to the metal film
15
is an upper-direction electric field. In addition, assume that polarization which is positive on the silicon film side and negative on the metal film side is under-direction polarization, and polarization which is negative on the silicon film side and positive on the metal film side is upper-direction polarization. Furthermore, assume that under-direction polarization (remanent polarization point) corresponds to a “1”-state (“1”-programming state), and upper-direction polarization (remanent polarization point) co

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