Semiconductor memory having sub-word line replacement

Static information storage and retrieval – Read/write circuit – Bad bit

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36523003, 36523006, 371 102, G11C 700

Patent

active

055815081

ABSTRACT:
In a semiconductor memory apparatus having a row decoder classified by main word lines and word lines, the number of spare lines for a defect is increased without increasing the number of spare main word lines. The area of a redundancy circuit is minimized to improve the yield of chip. Normal and spare memory blocks each including a plurality of memory cells are each divided so that replacement may be effected without increasing the number of spare main word lines even when defective addresses associated with a plurality of normal main word lines take place.

REFERENCES:
patent: 5033024 (1991-07-01), O'Connell et al.
patent: 5060197 (1991-10-01), Park et al.
patent: 5255228 (1993-10-01), Hatta et al.
patent: 5299161 (1994-03-01), Takeuchi et al.
patent: 5379258 (1995-01-01), Murakami et al.

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