Semiconductor memory having sub-party cell array error...

Details Semiconductor memory having sub-party cell array error... Semiconductor memory having sub-party cell array error...

2008-04-29

2008-04-29

Louis-Jacques, Jacques (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S703000

Reexamination Certificate

active

11092704

ABSTRACT:
Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data according to read data that are simultaneously read from the first and second regular cell arrays. A main parity generation circuit generates according to sub parity data parity data in common to the regular cell arrays, is not disposed in a distributed manner but disposed corresponding to the parity cell array. Thus, the layout design, layout verification, and so forth of a semiconductor memory can be prevented from being complexed. As a result, the parity generation circuit can be optimally laid out, decreasing the development time and defect analysis time for the semiconductor memory can be decreased.

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patent: 7032142 (2006-04-01), Fujioka et al.
patent: 62-119800 (1987-06-01), None

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