Semiconductor memory having space-efficient layout

Details Semiconductor memory having space-efficient layout Semiconductor memory having space-efficient layout

1997-09-26

1998-11-03

Nelms, David

Static information storage and retrieval

Read/write circuit

For complementary information

365207, 365208, 365 51, G11C 700, G11C 702, G11C 502

Patent

active

058319123

ABSTRACT:
The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.

REFERENCES:
patent: 5216634 (1993-06-01), Takano et al.
patent: 5313426 (1994-05-01), Sakuma et al.
"A 286mm.sup.2 256Mb DRAM with X32 Both-Ends DQ", by Watanabe et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, pp. 567-574.

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