Semiconductor memory having redundant cells

Details Semiconductor memory having redundant cells Semiconductor memory having redundant cells

1995-05-03

1996-09-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523002, 36523008, G11C 700, G11C 800

Patent

active

055555225

ABSTRACT:
A semiconductor memory comprising a flip-flop circuit, a redundant memory cell row and column, a specific address detecting gate, a transistor, a sense amplifier and a data output buffer. The receipt of a supply potential causes the flip-flop circuit to generate previously stored output status representing the use or the nonuse of the redundant memory cell row and column. Upon detection of a specific address by the specific address detecting gate, the transistor effects a switching operation causing the output status generated by the flip-flop circuit to be output to the outside via the transistor, sense amplifier and data output buffer. This allows the use or the nonuse of the redundant bits to be verified efficiently.

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"A 7-NS 1-MB BICMOS ECL SRAM with Shift Redundancy", IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.

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