Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1992-06-01
1995-07-04
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, 371 211, 371 101, G11C 2900
Patent
active
054306787
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor memory and more particularly to a memory having a function of performing a reliability test (drain stress test) or a burn-in test for learning data holding characteristics of drains of memory cells.
BACKGROUND ART
In an EPROM (Electrically Programmable and Erasable ROM) type of semiconductor memory, the commonly used type of memory cell is constructed from a transistor having a double-gate structure comprised of a control gate and a floating gate. To write data into this type of memory cell, a high potential (write potential VPP) is applied to each of a word line connected to the control gate and a bit line connected to the drain. The source is fixed at ground potential.
As a result of the application of the high-potential, a high electric field is produced in the neighborhood of the drain in the channel region of the memory cell, generating channel hot electrons. The hot electrons are injected into the floating gate by the high potential applied to the control gate. The hot electrons injected into the floating gate cause an increase in the threshold of the memory cell seen by the control gate, thereby allowing data to be stored.
FIG. 1 illustrates a portion of an EPROM in which a plurality of memory cells, having such a structure as described above, are arranged in an array. In FIG. 1, M1 through M4 denote memory cells, WL1 and WL2 denote word lines, BL1 and BL2 denote bit lines, 1A and 1B denote column decoders, 2 through 5 denote decode signals from the column decoders, and 6 denotes a row decoder. D1, D2, H1, and H2 denote bit line select transistors, and S denotes a transistor for writing a data in a memory cell in responsive to a predetermined signal (write transistor).
In normal write mode and read mode, in order to select one of the bit lines, the bit line select transistors D1, D2, H1, H2 are selectively driven by decode signals 2-5 from the column decoders 1A and 1B.
Suppose now that the memory cell M1 is written into. Then, the bit line BL1 and the word line WL1 are selected with the result that they are supplied with the high potential. At this time, the other memory cell M2 having its drain connected to the selected bit line BL1 and its control gate maintained at ground potential is in a nonselected state, but its drain is supplied with the high potential. If the number of memory cells connected to one bit line is N, (N-1) cells are placed in such a state. When memory cells are in such a state, electrical stress is applied to their drains. In cases where the quality of their gate oxide layers is poor, the leakage of electrons injected into their floating gates may occur, and thus data that has be written into once may be erased.
Therefore, a reliability test is made to study data holding characteristics of drains of memory cells. This test is performed by applying a high potential to the bit lines and putting the word lines in the nonselected state after all the memory cells have been written into. In order to perform the test on all the memory cells, it is required to test 2.sup.n bit lines when the number of column address pins is n. If, in this case, the test were repeated for each of the bit lines, the overall test time would become extremely long. To reduce the test time, therefore, conventional EPROMs have been equipped with an internal test function. In a test mode using this internal test function, all the decode signals output from the column decoders 1A, 1B in FIG. 1 are set to a high ("H") level, and all the bit-line select transistors D1, D2, H1, H2 are simultaneously rendered conductive. Further, the drain and gate of a write transistor S is applied the high write potential VPP as in the case of the writing of data.
At this time, the gates of the memory cells M1, M2 connected to the bit line BL1 are both at ground potential, so that they are both nonconductive. The same potential is applied to the drains of the memory cells. Subsequently, a check is made for reliability. Such is also the case with other bit lines
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Miyamoto Junichi
Tomita Naoto
Kabushiki Kaisha Toshiba
Le Vu
Popek Joseph A.
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