Semiconductor memory having redundancy memory cells

Details Semiconductor memory having redundancy memory cells Semiconductor memory having redundancy memory cells

1996-12-06

1998-06-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

365104, G11C 700

Patent

active

057611394

ABSTRACT:
A redundancy memory cell array is arranged at an end of a main memory cell array in the column direction. Common bit lines and common column lines are arranged on the main memory cell array and the redundancy memory cell array. A disconnection circuit is arranged between the main memory cell array and the redundancy memory cell array for connecting or disconnecting bit lines or column lines. A column selection switch is arranged at an end of the redundancy memory cell array. A redundancy circuit disconnects bit lines or column lines by means of a disconnection circuit when an address signal specifies a defective address.

REFERENCES:
patent: 5124948 (1992-06-01), Takizawa et al.
patent: 5179536 (1993-01-01), Kasa et al.
patent: 5535161 (1996-07-01), Kato
patent: 5555212 (1996-09-01), Toshiaki et al.

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