Semiconductor memory having redundancy circuit for relieving def

Details Semiconductor memory having redundancy circuit for relieving def Semiconductor memory having redundancy circuit for relieving def

1989-07-06

1991-06-04

Static information storage and retrieval

Read/write circuit

Bad bit

371 101, G11C 700, G11C 2900, G06F 1100

Patent

active

050219448

ABSTRACT:
A method and apparatus for quickly masking defective memory elements with substitute memory elements includes first and second memory blocks. The first memory block includes a first memory array and a second spare memory array. The second memory block includes a second memory array and a first spare memory array. A first word from the first memory array is selected concurrently with a first substitute word from the first spare memory. An address signal is decoded and then compared with data representative of a defective word. In the event it is determined, as a result of this comparison, that the first word is defective, the first substitute word is then communicated to a common data bus. Alternatively, the first word is communicated to the common data bus.

REFERENCES:
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 4542486 (1985-09-01), Anami et al.
patent: 4656610 (1987-04-01), Yoshida et al.
Sasaki et al., "A 9ns 1Ms CMOS SRAM", 1989 IEEE International Solid-State Circuits Conference, Session 2, Feb. 15, 1989, pp. 34-35.
Fitzgerald et al., "Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement", IBM Jrnl. of Research Development, vol. 24, No. 3, May 1980, pp. 294-297.

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